ADS1220: Difference between operation with and without RDATA command.

Part Number: ADS1220

Tool/software:

Hello,

I'm using ADC in continuous conversion mode. In my application, the period of reading data operation is much longer than the period of ADC data update. For that reason on the logic analyzer, I'm able to observe short periodic high states of the nDRDY line between readings which might interfere with data reading. From my understanding, it will work following way in both ways of data reading:

- When triggering read with RDATA command it doesn't matter if the read is triggered on nDRDY state low/high/toggle. It always returns correct and consistent data. When reading takes place during periodic data update nDRDY state indicates if ADC provides old or new data.

- For the SCLK mode only information in the datasheet that I found is that the reading shall be synchronized with the falling edge of nDRDY line. But there is no information about the side effects of reading in different states. 

So my questions are about the potential side effects of both ways of reading:

1. What will happen when reading data using the first SCLK rising edge when nDRDY high state?

2. What will happen when a data update (nDRDY pulse) takes place during SCLK rising edge data reading?

3. What will happen when reading data twice in a row using SCLK rising edge method? (Second read in state high)

4. Are there any other side effects of both reading methods that I should be aware of?

Thank you for your help.

Regards,

Sebastian

 
  • Hi Sebastian,

    I will take a look at this and get back to you by next Monday.

    Best Regards,

    Angel

  • Hi Sebastian,

    DRDY indicates when a new conversion result is ready for retrieval. When DRDY falls low, new conversion data are ready. DRDY transitions back high on the next SCLK rising edge. When no data are read during continuous conversion mode, DRDY remains low but pulses high for a duration of 2 · t(MOD) prior to the next DRDY falling edge. The DRDY pin is always actively driven, even when CS is high.

    The RDATA command loads the output shift register with the most recent conversion result. This command can be used when DOUT/DRDY or DRDY are not monitored to indicate that a new conversion result is available. If a conversion finishes in the middle of the RDATA command byte, the state of the DRDY pin at the end of the read operation signals whether the old or the new result is loaded. If the old result is loaded, DRDY stays low, indicating that the new result is not read out. The new conversion result loads when DRDY is high.

    Data is read using SPI Mode 1: CPOL=0, CPHA=1, so the data is clocked in on the falling edge of SCLK. 

    You can learn more about the details of SPI here: SPI communication basics (modes) | Video | TI.com

    Maybe providing a diagram/more details of where there is confusion on this will be useful in case further explanation is needed.

    Best Regards,

    Angel

  • Hello Angel,

    I'm interested in a case when the DRDY pin is not monitored and the RDATA command is not used. Such a mode of operation is not described in the datasheet.

    What information will be available on the MISO line when on the MOSI line the 4 bytes of 0xFF (no command) will be transmitted and DRDY will be in unwanted states?:

    1. "DRDY remains low but pulses high for a duration of 2 · t(MOD) prior to the next DRDY falling edge" What will happen when the pulse is observed during active SCLK? I know that with the first SCLK DRDY will go to high state and for that reason below picture is not correct but I want to describe the event which is interesting to me. 

    2. What will happen when data is not ready during active SCLK?

    Regards,

    Sebastian

  • Hi Sebastian,

    Let me take a closer look at this and I'll get back to you tomorrow.

    BR,

    Angel

  • Hi Sebastian,

    1. "DRDY remains low but pulses high for a duration of 2 · t(MOD) prior to the next DRDY falling edge" What will happen when the pulse is observed during active SCLK? I know that with the first SCLK DRDY will go to high state and for that reason below picture is not correct but I want to describe the event which is interesting to me. 

    If new data is ready while doing a data read, the data being read will correspond to the previous conversion. The new conversion data will be loaded onto the data buffer once the data is done being read. DRDY will remain high during the data reading, and will go low once the previous data is read. Then the new conversion data can be retrieved in the next data read. 

    What will happen when data is not ready during active SCLK?

    When the new conversion data is not ready when doing a data read, you will simply read out the data from the previous conversion, as the conversion data is stored in the internal data buffer and is replaced once the new conversion data is ready.

    Best Regards,

    Angel

  • Hello Angel,

    Thank you for your response. So I can assume 2 things. Please correct me if I'm wrong:

    1. There are no benefits of using RDATA command over using SCLK without command. Both solutions ensure that data will be consistent. The only difference is that RDATA approach is slower as it requires a 4bytes transfer vs 3bytes for the SCLK approach. In other aspects they are identical. 

    2. There is no need to monitor DRDY line if the period of data reading is much bigger the period of data update. The device is designed in a way that at any time it provides consistent data.

    Regards,
    Sebastian

  • Hello Sebastian,

    Correct, both methods are equally valid for reading out conversion data.

    The device is designed so that data can always be read without concern of data corruption. DRDY helps you determine whether the data being read is new data or data from the previous conversion.

    Best Regards,

    Angel