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ADC3683-SP: CLK VID impact and minimum value

Vincent Renaud
Prodigy 40 points
Part Number: ADC3683-SP

Tool/software:

Hello,

I have two questions regarding the amplitude of the sampling clock signal.

We want to drive the sampling clock signal with an FPGA. Since we have a few inches of trace between driver and receiver, we need to terminate the signal. We quickly run into issues with the maximum current of the FPGA IOs (if using standard 50 ohm termination), or require high impedance traces that are harder to manufacture. The typical amplitude is listed at 1Vpp, but there are no minimum/maximum. We might be interested in using AC-coupled differential LVDS signals to drive the sampling clock, allowing us to use 100 ohm differential traces and achievable FPGA IO current. This seems to be supported based on the graph below.

My questions are the following:

1) What is the mechanism explaining how sampling clock amplitude affects the signal quality? Is it because lower clock amplitude increases the triggering jitter which increase noises on a sinusoidal waveform? I ask this question because we plan to sample a square wave signal and we are able to sample away from the edges. That makes our application more robust to triggering jitter than sampling a sinusoidal signal which constantly changes.

2) Can the amplitude range listed above be considered "recommended values"? What I mean by that is that if we accept the performances at 0.5Vpp, is it a sustainable/glitch-free/repeatable operating point? The fact that the datasheet does not mention a minimum amplitude signal makes me wonder.

Based on your answer we will be able to decide if using LVDS is a viable solution.

Best regards,

Vincent

  • 0
    TI__Mastermind 29940 points

    Hi Vincent,

    Based on your first comment, I have more concerns there then the questions you have.

    Using an FPGA as the sampling clock would highly degrade the performance of the ADC. The jitter on FPGA clocks is fairly high and this will decrease the dynamic range.

    I would consider using a better clocking device if your requirements are close achieving the datasheet performance of the ADC3683-SP.

    Here are my comments to your questions below in RED.

    Regards,

    Rob

    1) What is the mechanism explaining how sampling clock amplitude affects the signal quality? RR: the clocking signal quality needs to be low in noise and high in slew (large in amplitude) in order to achieve the converter's rated performance. Is it because lower clock amplitude increases the triggering jitter which increase noises on a sinusoidal waveform? RR: lower clock amplitudes effectively take a longer time moving thru the sampling threshold, this allows more noise to be convolved to the output spectrum of the ADC. I ask this question because we plan to sample a square wave signal and we are able to sample away from the edges. That makes our application more robust to triggering jitter than sampling a sinusoidal signal which constantly changes. RR: square or sine waves are fine, the ADC doesn't care, it just needs the clock to be very repetitive in low noise and high slew.

    2) Can the amplitude range listed above be considered "recommended values"? RR: yes, What I mean by that is that if we accept the performances at 0.5Vpp, is it a sustainable/glitch-free/repeatable operating point? RR: yes, this is repeatable. The fact that the datasheet does not mention a minimum amplitude signal makes me wonder. RR: not sure why there isn't a min spec there for the commercial device, we will be putting a min on the space version.

    Based on your answer we will be able to decide if using LVDS is a viable solution. RR: LVDS will work, however, it will not deliver the best performance. Typically we recommend a PECL style interface, this will give the best slew to the ADC.

    As a side note, there is plenty of information on clocking out there on the web, but if you need recommendations please let me know and I am happy to forward a few recommended links on sampling clocks vs. performance.

  • 0 in reply to Rob Reeder
    Prodigy 40 points

    Thank you Rob for the quick reply. I have some following questions based on your answers:

    1) What is the recommended maximum jitter on the sampling clock? There is a jitter recommendation for the DCLKIN, but I could not find one for the sampling clock.

    2) What happens if we go outside the maximum jitter on the sampling clock? Is it a functional loss or only a loss in performance ?

    For reference, our application is more reliant on high sampling rate with good amplitude level measurements than on good frequency characteristics. The added noise caused by aperture jitter affecting FFT results does not impact our application. We care more about what we could call "DC parameters", like DNL/INL/Thermal noise/Quantization noise.

    If those parameters are not affected by using a lower amplitude/higher jitter sampling clock signal, using the LVDS from an FPGA could be a simple solution that does not require additional components.

    I would still be interested in the links you mentioned about sampling clock vs performance to confirm I understand the tradeoff correctly.

    Best regards,

    Vincent

  • 0 in reply to Vincent Renaud
    TI__Mastermind 29940 points

    Hi Vincent,

    If your application frequency is low and you are effectively doing a time domain data capture to display your measurement, you might be okay.

    With increasing noise or jitter on the clock, this will raise the noise floor of the ADC, therefore, lowering the dynamic range of resolution of your display.

    The FPGA is certainly okay way to clock the ADC, it just won't yield datasheet performance.

    Here are a few links for further reading:

    https://www.analog.com/media/en/analog-dialogue/volume-42/number-1/articles/analog-to-digital-converter-clock-optimization.pdf

    https://www.analog.com/media/en/technical-documentation/application-notes/AN-501.pdf

    https://www.ti.com/lit/an/slyt379/slyt379.pdf?ts=1722537116935&ref_url=https%253A%252F%252Fwww.google.com%252F

    https://www.tij.co.jp/lit/an/slyt389/slyt389.pdf?ts=1722537174451&ref_url=https%253A%252F%252Fwww.google.com%252F

    https://www.ti.com/lit/an/slyt422/slyt422.pdf?ts=1722537185225&ref_url=https%253A%252F%252Fwww.google.com%252F

    Regards,

    Rob

  • 0 in reply to Rob Reeder
    Prodigy 40 points

    Thank you again for the quick response and the links. I will mark this thread as resolved.