ADC12QJ1600EVM: ADC12QJ1600

Hi Giora,

The sampling clock jitter would have to be very high.

Is the serdes loosing lock? Is that the reason for your question?

Thanks,

Rob

Hello Rob,

We intend to change the Oscillator - CVHD-950-50.000 - that reside on the EVM with

AX3PAF1-100.00 ( from Abracon) with 211fs (typ.) - RMS Phase Jitter (12kHz -20MHz BW) ,Vdd= 3.3V .

Is it OK?

AX3-1578477.pdf

Regards,

Giora

Hello Rob,

Any comment?

Regards,

Giora

Hi Giora,

This Abracon device is 4x the jitter than the Crystek.

It would really be good to understand the following before I can say what the performance degradation would be.

On the EVM, is the new oscillator being connected to the ADC direct? or is this part of a clocking path. There are multiple ways to implement the clock on the EVM. I have no idea which one is being used.

Second, please give me the analog input frequency range that will be used for this application. This will help me a understand on how much SNR degradation will take place with this new oscillator.

Thanks,

Rob

Dear Rob,

1. On the EVM The oscillator is connected directly to the ADC.

2. On our board the oscillator (LMK6DA10000ADLFR or CCPD-575X-20-100.000) is connected to a driver

    (8T39S11ANLGI) that distribute the clock signal to X8 ADCs clocks inputs.

3. Signal BW is 100Mhz.

    What will be the SNR degradation and will we have problem with the locking of the 12.375 Gbit/s

     (Jmode8, 66/64bit at 1Ghz sampling)?

crystek_ccpd575x2080000_apr22_xonlink.pdf

REN_8T39S11A_DST_20230417.pdf

lmk6d.pdf

Sincerely,

Giora