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ADS1282: Calibration sequence clarification and SDATAC questions

Vincent Renaud
Prodigy 40 points
Part Number: ADS1282
Other Parts Discussed in Thread: ADS1285

Tool/software:

Hello,

I have some questions about the calibration procedure shown below.

I want to further understand each command and their role.

1) Why is SDATAC first sent if it is followed later by a RDATAC? Is it because SDATAC must be sent before any other command (SYNC or R/W reg or others)?

2) Why is the SYNC signal needed?

3) I understand that the RDATAC and 64 data period is to allow proper settling of the FIR filter. Is that correct?

4) Why is SDATAC needed again? Is it because OFSCAL/GANCAL must be sent only when we are not in read continuous?

5) Do we need to do OFSCAL before GANCAL or is the order unimportant? I assume offset removal is important for the gain calculation, but I couldn't find confirmation for this.

I would have expected this simpler sequence to work:

1) Wait for settling of reference voltage and input voltage

2) Send the OFSCAL/GANCAL command

3) Wait 16 drdy cycles

I have another question about SDATAC:

1) Is it necessary to go in SDATAC mode for any command, whether is it read or write? I expected it to be needed only for read command because of the sharing of the dout signal, but the further I read, the more I understand that any spi command needs to be done in SDATAC mode.

Thank you,

Vincent

  • 0
    TI__Mastermind 40710 points

    Hello Vincent,

    1) Why is SDATAC first sent if it is followed later by a RDATAC? Is it because SDATAC must be sent before any other command (SYNC or R/W reg or others)?  This sequence of commands for the calibration provides the most consistent timing and has been validated.  In general, you do not need to send SDATAC before most commands, per table 20.

    2) Why is the SYNC signal needed?  This forces /DRDY high, ensures the digital filter is fully settled with the input short or full scale input levels before starting the calibration.

    3) I understand that the RDATAC and 64 data period is to allow proper settling of the FIR filter. Is that correct?  Yes, this is correct.  We need to make sure the filter is fully settled with either the 0V or full scale input levels for accurate calibration results.

    4) Why is SDATAC needed again? Is it because OFSCAL/GANCAL must be sent only when we are not in read continuous?  We need to make sure that the first reading after the OFSCAL/GANCAL is not corrupted.  The best way to do this is to go ahead and stop continuous readings, and then restart after the OFSCAL/GANCAL command has been sent.

    5) Do we need to do OFSCAL before GANCAL or is the order unimportant? I assume offset removal is important for the gain calculation, but I couldn't find confirmation for this.  Yes, the OFSCAL command simply stores the averaged 0V input result into the offset register.  This value is then applied to the average readings during the GANCAL command.  The math used to calculate the gain value assumes there is no offset error.

    1) Is it necessary to go in SDATAC mode for any command, whether is it read or write? I expected it to be needed only for read command because of the sharing of the dout signal, but the further I read, the more I understand that any spi command needs to be done in SDATAC mode  No, in general, you only need to send the SDATAC before sending a RREG or RDATA command, but the offset/gain calibration should follow Figure 60 for consistent results.

    You may want to look at the ADS1285, which is a newer generation device.  The offset/gain calibration commands are much simpler with this device, as the ADC takes care of all the details.

    Regards,
    Keith Nicholas
    Precision ADC Applications

  • 0 in reply to Keith Nicholas
    Prodigy 40 points

    Thank you Keith for the answer.

    It leads me to other questions.

    1) You say that sending the SYNC command before the RDATAC is done so that DRDY turns high. If I understand correctly, this is to be able to just wait until DRDY falls back to 0 to know that we are settled. It won't toggle during this time. Is that correct?

    2) If Q1 is correct, I suspect it only works on pulse-sync mode, not continuous-sync mode, is that right? We are planning to use the device in continuous-sync mode. In continous-sync mode, I suspect we need to manually count the 64 DRDY to do the same logic am I correct?

    3) If DRDY counting is needed in continous-sync mode, it might be simpler in our case to simply introduce a fixed delay, longer than the settling time and the 64 DRDY of settling. Would this work? For example :

    Step 1) Configure internal short.

    Step 2) Wait a long duration that guarantees settling (1 second for example).

    Step 3) Directly going to the second half of figure 60 (SDATAC, GANCAL, etc).

    4) When you say that SDATAC is needed to be sure that GANCAL is not corrupted, what type of corruption are we talking about? Is it to prevent a data being clocked out during the GANCAL command? (for example if DRDY falls in the middle of the GANCAL byte command) or is it something else?

    5) What explains the 64 and 16 DRDY delay in the procedure? I suspect the 64 is based on the Tdr with FIR, even though it is not exactly 64 (62.98/fdata). But there is no mention for the 16 DRDY. Is it because DRDY is driven differently following GANCAL/OFSCAL? And if so, how does it compare between continuous and pulse sync modes?

    Thank you for your help,

    Vincent

  • 0 in reply to Vincent Renaud
    TI__Mastermind 40710 points

    Hi Vincent,

    1&2. Yes, this step ensures the filter is fully settled and /DRDY falling edge indicates when this process is complete.  The SYNC pin must be held high during the calibration procedure and you need to be in pulse-sync mode to use the SYNC command.  After calibration, you can change to continuous-sync mode and apply your SYNC clock signal to the SYNC pin.

    3. Run the calibration in pulse-sync mode, wait for /DRDY falling edge.  After calibration is complete, change to continuous-sync mode and apply your SYNC signal to the SYNC pin.  You cannot run the calibration routine in continuous-sync mode.

    4.  We need to stop continuous conversions before the GANCAL command to meet the internal timing requirements of the ADC.  Once you send the GANCAL, the ADC averages the next 16 readings used to calculate the gain coefficient.

    5.  64 conversion periods are necessary to reset the internal filter, or fully settle.  The settling time of the filter is 62 conversion periods, but there is additional overhead timing needed for the SYNC command, which extends the total time to 64 conversion periods.  The 16 DRDY conversion periods are the 16 conversion results that are averaged together and used to calculate the gain coefficient.

    Regards,
    Keith

  • 0 in reply to Keith Nicholas
    Prodigy 40 points

    Ok this seems to clarify everything to me. The sequence involves a lot of different functionalities of the component (sync mode, sync source, order of operation, SDATAC vs RDATAC, etc). To help myself I wrote a sequence that should work based on the datasheet and your feedback. Can you confirm this sequence is functional?

    1) Pull Sync pin HIGH to be able to use SYNCCMD later.

    2) Update config0 and config1 register to change the mux to short the input as well as be in pulsed-sync mode

    3) Send SDATAC - SYNCCMD - RDATAC. The RDATAC done after the SYNCCMD pulls the DRDY high, because of the pulsed-sync mode.

    4) Wait until DRDY falls to 0. This guarantees the proper settling of the FIR filter. No need to manually count delay.

    5) Send SDATAC - OFSCAL - RDATAC. Again, RDATAC done after OFSCAL makes the DRDY go high, even if we did not send the SYNCCMD again. It will return to 0 once ofscal is completed.

    6) Wait until DRDY falls to 0. At this point, I expect the OFC registers to be updated to a new value and the offset to be removed from any subsequent readings (if I do not update the OFC registers again).

    7) Re-do step 2 to 6, with the a full scale mux configuration on step 2 and the GANCAL instead of OFSCAL on step 5. GANCAL must be done after OFSCAL because GANCAL assumes 0 offset error.

    8) Restore config0 and config1 registers to their initial value. At this point, The calibration is completed and used. I can drive the sync pin as required in our application.

    Thank you for your help,

    Vincent

  • 0 in reply to Vincent Renaud
    TI__Mastermind 41381 points

    Hi Vincent Renaud,

    Keith is out of the office, he will respond to your question by the middle of next week. Thanks for your patience

    -Bryan

  • +1 in reply to Vincent Renaud
    TI__Mastermind 40710 points

    Hello Vincent,

    My apologies for not getting back earlier.  At this point, I assume you were able to verify the above sequence. 

    Yes, the above procedure is correct and should work well in your system.  I would add that you may need to delay between steps 2 and 3 to make sure the input has settled.  This is not much of an issue with an internal short as this will settle very quickly, but applying an external full scale input may require some additional time to settle.  The amount of time required can be estimated by measuring the input with a scope if needed.  This will give you 1 sigma settling; for settling to within the noise limits, multiply by roughly 16x.

    Regards,
    Keith