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Original question:

AFE7222 clock input level requirement

AFE7225: Differential Clock Input Level

Brady
Prodigy 20 points
Part Number: AFE7225

Tool/software:

I was looking through SLOA229 ("Working with DC coupled Clock pins in AFE7225") and saw that it was mentioned that the VCM buffer on the chip may not come up if the input signal is not large enough in amplitude to allow for proper clock detect. This application note seems to focus on single-ended clock input, but this old thread seems to imply there are also problems with differential inputs.

In my design I am planning to drive the clock inputs with an AC-coupled LVDS signal (~ 400 mVpp single-ended) and am wondering if I must include writing to register 0xD8 bit 5 as part of the initialization sequence in order to reliably initialize the VCM buffer, or if this behavior has been fixed since that original thread was created?

  • 0
    TI__Mastermind 27420 points

    Hi Brady,

    I will have to do a bit of research on this as this part is old, your LVDS clock should be fine.

    However, if you can use a DIFF PECL style clock swing, that is always better in performance for any converter.

    Please give me a few days to see if this register is needed or not.

    Regards,

    Rob

  • 0 in reply to Rob Reeder
    Prodigy 20 points

    Is there a spec for common-mode range that can be input to the clock buffer?

    Instead of AC coupling the differential signal, I could instead DC couple the clock (Vcm ranges from 0.8 - 1.0 V) which would mean the common-mode bias for the AFE input buffer is provided by the clock output instead of the internal Vcm buffer, and any difference between internal/external Vcm is dissipated in the internal 5 kOhm resistor.

  • 0 in reply to Brady
    TI__Mastermind 27420 points

    Hi Brady,

    I would stay with an AC coupled input to the clock pins. I reread your post, are you planning to drive the clock single-ended, SE, or differential, DIFF.

    If DIFF, then there is no need to worry about this setting.

    Regards,

    Rob

  • 0 in reply to Rob Reeder
    Prodigy 20 points

    We are driving it with differential, I was just under the impression from the tagged thread in the original post that the lack of Vcm bias could still be an issue. 

    If the Vcm buffer is down at startup (due to no clock detect) what is biasing the differential buffer inputs?

  • 0 in reply to Brady
    TI__Mastermind 27420 points

    Hi Brady,

    Let me double check with design and get back to you on this.

    Please give me a few days.

    Thanks,

    Rob

  • 0 in reply to Rob Reeder
    TI__Mastermind 27420 points

    Hi Brady,

    I spoke to design on this, the Input Clock pins (CLKINP and CLKINN) are self biased by device at 0.95V through an internal VCM buffer.

    However, the VCM buffer needs a valid signal at CLK pins to generate required common mode voltage.  If clock signal’s amplitude is not large enough after power up, VCM buffer will not start.

    To avoid such situation, dependency of VCM buffer on input clock can be removed by setting register bit <5> in address 0xD8 to ‘1’.

    Regards,

    Rob