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Original question:

Direct Digital Synthesizer that can chirp 0-2 GHz in <10us

DDS39RFS10: 1 Gbps JESD204B with standard LVDS SerDes or DDS based IQ Modulation

BH
Prodigy 50 points
Other Parts Discussed in Thread: DAC39RFS10, DAC39RFS12

Tool/software:

Need very little signal BW (No more than 2 MHz), just be able to place the carrier anywhere upto 6 GHz. I see this device has 256x Interpolation so is this possible:

  • 50 MHz I/Q data over two lanes
  • 1Gbps per lane (50 * (16+4)) after encoding
  • 50 * 256 = 12800 MHz DUC output

Now there seem to be a lot of constraints around JMODE and interpolation rate (7.4.2 JESD204C Interface Modes), that is one confusing table. So whatever the constraints, what settings would I need for: Using the lowest possible serial bit rate (Fbit), limited lanes and simplest serialization on the TX side. I plan to implement it using a MIPI capable LVDS SerDes transmitter, which supports 8b/10b encoding. Both the FPGA and DAC will be run from the same clock source/frequency locked. No scrambler, hopefully no multi-lane sync, no cross-device sync or any other phase sync features.

Aside from this, I am also curious about the DDS mode with the Fast 4-bit SPI. Can we implement arbitrary modulations using the NCO + multiple DUCs? Any way to covert a low sample rate IQ data to... whatever is possible with freq, phase and amplitude modulation from bonding multiple DUC outputs.

  • 0
    TI__Expert 3550 points

    Hello, 

    JESD as you have stated quite a complicated standard to use. Please note that this DAC only has JESD modes and does not use LVDS input modes. It appears you want to use 8b10b encoding so we'll stick with those. 

    So first you would want to set your DAC update rate (FDAC). This is the clock you give the DAC. The DAC39RFS10 can operate up to 10.24GSPS (Fdac = 10.24GHz, the DAC39RFS12 can operate up to 12GSPS (12GHz). 

    Since you mentioned the DAC39RFS10 we'll start with the maximum Fdac for that device (10.24GSPS). 

    You say 50MHz I/Q bandwidth so I'll assume you mean +/-50MHz so a total of 100MHz bandwidth before up conversion. 

    At 10.24GSPS you could interpolate by 64 to get 160MSPS of input data. The interpolation filters have an 80% passband so at 160MSPS you would get 128MHz of effective bandwidth (+/- 64MHz). 

    This would allow you to use JMODE4 and JMODE5. JMODE4 would use 2 lanes at 3.2Gbps and JMODE5 would 1 lane at 6.4Gbps. These rates are both after the encoding. 

    Regards, 

    Matt

  • 0 in reply to Matthew Kramer
    Prodigy 50 points

    So the higher interpolation rates (128, 256) only help with pushing more streams per lane and can't lower the input BW / data rate. I think a spec/note can be added to the datasheet saying: minimum input BW = Fdac/64 so we can arrive at the same conclusion without the need for complicated serdes calculation. It does mention a minimum Fserdes of 781.25 Mbps, so that would allow for minimum Fdac of 2.5 Gsps at 64x (when JESD is needed).

    I did mean 50 MHz BW or +/- 25 MHz, 160 MSPS is 3.2x that. So, not an option for our application.

    Should I make a separate post for DDS mode feasibility, are there any app notes that details modulation possibilities with just NCO + multi DUC?