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Original question:

DAC8742H: Does DAC8742H has passed the physical layer test of hart foundation

DAC8742H: Does DAC8742H has passed the physical layer test of Fieldbus foundation

Thong Tuan HUYNH
Prodigy 10 points
Part Number: DAC8742H
Other Parts Discussed in Thread: TIDA-01504

Tool/software:

I am developing a fieldbus application using the DAC8742H. The transmitter driver board was taken from the DAC8742H datasheet. However, when I went through the Physical layer tests, it failed at the Receive Jitter tolerance test. I believe the problem is from the DAC8742H itself, because the BUS+ was connected directly to the MOD_IN of the DAC8742H (via DC removal capacitor). I checked the DAC8742H datasheet and found out the jitter tolerance is +-3.2us

However, when setting the jitter of my reference transmitter to 3.2us, the DAC8742H gets only 95-97% of every 1000 transmitted messages. 

So my question is:

  1. Is there any "margin of safety" for the 3.2us jitter tolerance stated in the datasheet? For example, how likely/many percentages, we receive a message correctly if the jitter is 3.21us?
  2. Is the DAC8742H, or any relevant design, like TIDA-01504, passed the Physical layer test?
  • 0
    TI__Mastermind 33168 points

    Hello, 

    Joseph will review your questions and provide a response soon. 

    Best,

    Katlynne Jones

  • 0
    TI__Guru* 94185 points

    Hi,


    I'm not sure about the origin of the jitter tolerance specification. For min-max specifications, we generally have some amount of guard band to make sure we're not close to a specification edge case. However, for jitter tolerance, the value may be based on some timing related to an internal clock. I don't think there is a way to guess how likely a message would be received if the jitter is over the specification.

    As for the testing of the device in a Fieldbus application, TI had started work on a design for PAFF but it was stopped due to priority changes in the group. There was a test circuit and TI had worked on a test board and a firmware stack with a third party. As I understand it, the hardware passed all physical layer tests except one test on the input impedance frequency response. There isn't any information on how it did not pass, and any modifications needed make the change.

    There is an older post that does give some information about an example circuit here:

    https://e2e.ti.com/support/data-converters-group/data-converters/f/data-converters-forum/821316/dac8740h-the-reference-design-of-field-transmitter-with-profibus-pa


    Joseph Wu

  • 0 in reply to Joseph Wu
    Prodigy 10 points

    Hi Joseph, great to know that the chip passed all the physical test, including the jitter tolerance test. So it is strange that my jitter test was fail. Could you please share the report on your jitter tolerance test? Did you successful receive 100% of 1000 packages with jitter of +-3.2ms 

  • 0 in reply to Thong Tuan HUYNH
    TI__Guru* 94185 points

    Thong Tuan,


    I don't have a specific report for the jitter tolerance test. I do have a bunch of log files from a company that started the process of testing the board being developed for Fieldbus.

    To be clear, I'm not very familiar with Fieldbus and how it's tested, so I'm not sure exactly how to help with this question. and I don't know what each of these tests refer to. I'm much more familiar with the HART aspects of this device.

    Regardless, I can check on the origin on the jitter specification and get back to you.


    Joseph Wu

    TI-FF-V301.complete.results

  • 0 in reply to Joseph Wu
    Prodigy 10 points

    Dear Joseph

    Thanks for sharing the test log, but these test are likely relevant to the Datalink layer test, not the Physical test where we check the electrical characteristic of the devices.

    To shorten my question: Texas Instrument stated the chip can tolerance jitter of 3.2us, but my test showed the opposite. So I am asking for document/evidence/test procedure to check if I did something wrong, or the DAC8742H itself can NOT tolerance jitter of 3.2us. 

    Or could I understand that the jitter tolerance has never been tested at TI, but just come from theory/calculation based on the internal clock?

  • 0 in reply to Thong Tuan HUYNH
    TI__Guru* 94185 points

    Hi,

    I did talk to one of the digital designers, and this specification comes as a percentage of the clock rate (at 31.25kbps, that would be 32us for a bit, and 3.2us would be 10% of the bit period). He thinks that they were able to simulate a 4us jitter error without a problem. However, if the clock source is off, or has additional jitter, that would add to the error.

    Joseph Wu