ADC12DJ5200-SP: how to use clock chip LMX2594RHAR and LMK04828BISQE/NOPB

Hi  Chase,

    Thank you for your quickly reply! please review ADC and clock part schematic.

can you help me calculate LMK04828BISQE/NOPB based on my clock output, thanks!

Hi Chase，

    LMK04828 PLL2 also use external VCXO, so in my opinion, OSCin clock is reserve, right? I update sch, DCLKout clk all 260M, but SDCLKout7 and 9  clk are 40.625M, how is this achieve? I think SDCLKout clk is same as DCLKout clk?

    Thanks very much!

   DDH_1224.pdf

Moving this to the Clocking team to help comment.

Regards,

Rob

Hello Xiaoqiu, 
I am a bit confused on your question?
In your schematic I see both CLKinX & OSCIN are used. 
CLKINx path connects to PLL1 to drive a very clean VCXO normally used for jitter cleaning by utilizing a very narrow loop bandwidth to have the phase noise of the VCXO dominate and "jitter clean." PLL1 can also be used for frequency conversion as well if the ref clk does not have an integer relationship with the VCO frequency you need for CLK distribution. 

If your ref clock is extremely clean - you can directly feed a 260MHz CLK into OSCIN to create a 2600MHz VCO frequency (VCO-0) for PLL2 which can then be divided down to create the 10MHz clks. 

This 2600MHz VCO frequency can also be divided down to generate the 40.625MHz SYSREF CLKs. 

I am a bit curious - what is the purpose of the 32.5MHz clk at CLKin0? 
Best regards ,

Vicente 

HI Vicente flores prado,

      we want use LMX2594 ouput two chennel 5GHz clock to ADC12DJ5200RFAVV, input clock 156.25MHz, attachment is schematic and TICS file, please help me if right, thanks!

LMX2594.tcs

Hi Xiaoqiu, 

Please let us know the JMODE you are planning to use with the ADC.

I see the ADC's sampling clock frequency is 5.0GHz.

Regards,

Rob

Hi Rob，

     ADC use JMODE 45, thanks!

Hi Xiaoqiu,

I have looked over your schematic and TICS file, and it all looks good. It is configured for correct functionality for your use.

With respect to the LMK04828, let me say that your current configuration will work, but only if you are using single loop mode. You will need to input the reference clock that you want to synchronize to your VCO to the OSC_IN pin. I have attached an LMK04828 config that should be able to guide you through the process. 

lmk04828_clocktree.tcs

Thanks,

Michael

Hi  Michael,

     I want to use FTDI control TICS, but FTDI color is grey, can't choose, so can't use TICS program LMX2594, please help check, thank!

Hi Rob,

    We are debuging ADC12DJ5200RFAVV, voltage is 1.091V as VD11, 1.089V as VA11, 1.851V as VA19, when power up, no clock input(CLK+/-), initial power consumption is about 8W, when input clock 5G to ADC(CLK+/-), power consumption is about 19W, if the ADC work wrong? below is our schematic, please help review, thanks!

ADC12DJ5200RFAVV.pdf

Hi Xiaoqiu, 

I assume you mean 19W for the entire board?

Seems a little high, unless you are dropping alot of voltage/power across the LDOs or power supplies to get to 1.1V and 1.9V.

The schematic looks fine to me.

Regards,

Rob

Hi  Rob,

  The whole board power is 24W. there are two clock chips and two pcs ADC12DJ5200RFAVV on board, no clk to ADC12DJ5200RFAVV, whole power is 12W, 5G clk to ADC12DJ5200RFAVV, whole power is 24W. two clock chips power is 5W. so ADC12DJ5200RFAVV power is 19W.

  if ADC12DJ5200RFAVV work abnormal, power will be higher. voltage is 1.091V as VD11, 1.089V as VA11, 1.851V as VA19. that seems ok, not dropping a lot.

Hi Rob,

     please privide us ADC12DJ5200RFAVV code, we use this chip, need to software, thanks!

Hi Rob,

      please provide us JESD204C IP, use intel FPGA  AGIB027R31B and two pcs ADC ADC12DJ5200RFAVV, thanks!

Hi Rob,

     Datasheet ADC12DJ5200RFAVV, Jmode 45 lanes is different at two page side. which is correct?

Hi  Rob,

      Base on refference design of ADC12DJ5200RF EVM, resistance network is low pass filter, 8.66ohm-140ohm-8.66ohm, What is the signal bandwidth range?  please supply us internal capcitor and resistance on ADC input pin.

      Thanks!

Hi Rob,

      we use refer network and parallel 0.4pf capacitor to GND, parallel 50ohm resistance to GND. simulate result is not 300K to 8.2G. if we use wrong parameter? 

Hi Xiaoqiu, 

Use the analog input sparameters on TI.com on the 5200RF webpage. This would be a better way to do your simulation.

Regards,

Rob