DAC5675A-SP: Can the clock pins be driven with LVDS?

Tool/software:

This question has been asked before, but there seems to be conflicting answers. So I would like to get confirmation on whether the clock pins can be driven differentially with LVDS.

Per the DAC5675A datasheet, the clock differential input voltage, |CLK - CLKC| has a minimum of 0.4 Vpp and a maximum of 0.8 Vpp.

The LVDS driver has a differential output voltage of 250mV to 400mV.

The following post suggests that LVDS may not provide sufficient swing and that LVPECL is recommended:

https://e2e.ti.com/support/data-converters-group/data-converters/f/data-converters-forum/1055560/dac5675a-sp-driving-the-clock-pins-with-lvds-signal

However, this post suggests that LVDS is sufficient:

https://e2e.ti.com/support/data-converters-group/data-converters/f/data-converters-forum/1376494/dac5675a-sp-question-about-clk-clkc?tisearch=e2e-sitesearch&keymatch=DAC5675A-SP

Which one is correct? 

Thank you.