AFE58JD48EVM: Query regading the ADC sample MSB bit

Nitin Yadav

Part Number: AFE58JD48EVM
Other Parts Discussed in Thread: LMK04826, AFE58JD48

Tool/software:

Hi,

We planning to check the determinstic latency between JESD204B RX and ADC, I have a reference setup image we are planning to use for proving the deterministic latency.

But we facing some issue with the ADC sample MSB bit, if we capture the ADC_MSB bit the duty cycle is not constant always, also the rising and falling edge have some overlapping.
We are sending a sine wave as input to at different frequencies for testing but as we increase the frequency the overlapping increases. So can help us to debug this issue since if the duty is not constant we cannot say the signal is relaible for use to prove deterministic latency. I have attached the capture images at 5MHz.

5MHz

10 months ago

0 Sachin H K 10 months ago

TI__Expert 7725 points

Hi,

Based on the jesd subclass type Sync/sysref is used in JESD for alignment . But this signal gets latched on clock . Is your device clock , sync/sysref and signal you are generating are locked ?

0 Nitin Yadav 10 months ago in reply to Sachin H K

Prodigy 120 points

Hi Sachin,

The signal we are generating is independent from sysref and device clock, we are using JESD6600 as the square wave generator instead of generating it through FPGA.

0 Sachin H K 10 months ago in reply to Nitin Yadav

TI__Expert 7725 points

Nitin,

So you are comparing the MSB data from ADC with input signal ? Since clock and signal are not locked we need input signal reference to compare the ADC output data.

0 Nitin Yadav 10 months ago in reply to Sachin H K

Prodigy 120 points

Hi Sachin,

Yes we are comparing the MSB data with ADC input signal
I have attached our setup for your reference

I am not getting why we need to synchronize the signal generator to the JESD clock, and how this is creating this duty cycle changes.
Also, by "Since clock and signal are not locked we need input signal reference to compare the ADC output data" this you mean that we need to put trigger on the ADC input.

I check the measurements with putting the trigger on the ADC input and then comparing it with ADC_MSB bit still the edges are not clean there is jitter on the edges.

So can you help us to debug this issue.

0 Sachin H K 10 months ago in reply to Nitin Yadav

TI__Expert 7725 points

If your clock and signal source is not locked run to run it can have phase variation. Or signal frequency can drift very slightly over time . So to avoid these kind of issue generally reference out (usually 10MHz) is taken from one source and given to ref in of other source .

So you need to do this for clock source and signal source . Once that is done you should see repeatable data .

0 Nitin Yadav 10 months ago in reply to Sachin H K

Prodigy 120 points

Hi Sachin

Thanks for the input, we changed the source signal. Now we are generating the input signal from FPGA itself from same device clock and now we are not getting this this.

But, we are getting an another issue that when we measure the determinstic latency for the setup it remains almost constant but once in 5-6 power cycle we see a drift of 8ns. We are operating at 125MHz device clock, we changed the delay between the device clock and sysref from LMK but still we are getting this issue. Can you help us to debug this issue. I am attaching the scope waveform in both the cases for your reference.

with 8ns variation

without 8ns variation

0 Nitin Yadav 10 months ago in reply to Nitin Yadav

Prodigy 120 points

Hi,

Any update on this ?

0 Sachin H K 10 months ago in reply to Nitin Yadav

TI__Expert 7725 points

Nitin,

Sorry for the delay .

I see that b pointer threshold is different in these two picture . Am i missing something ?

125MHz one clock cycle is 8ns . This is indicating 1 clock cycle miss. How is sysref generated for FPGA ?

0 Nitin Yadav 10 months ago in reply to Sachin H K

Prodigy 120 points

Hi Sachin,

The pointer is set as per the blue waveform but the threshold reference it is taking from the upper waveform and intially the offset of input waveform is not zero due to power splitter in the path, so maybe due to that this threshold is coming negative

We are generating sysref, GTX clock, device clock and ADC sampling clock from the onboard LMK, I am using the following config file for the ADC eval board configuration

0 Sachin H K 10 months ago in reply to Nitin Yadav

TI__Expert 7725 points

Duplicate thread

e2e.ti.com/.../afe58jd48evm-query-regarding-deterministic-latency-one-device-clock-cycle-variation

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AFE58JD48EVM: Query regading the ADC sample MSB bit