Other Parts Discussed in Thread: LMK04826, AFE58JD48
Tool/software:
Hi,
We are testing determistic latency for AFE58JD48EVM with JESD204B RX IP on EFINIX FPGA, I have attached the setup we are using for your reference.
We are generating a 6.25MHz square wave from FPGA itself with device clock, LMK is used for both FPGA(device clock and SYSREF) and ADC (sampling clock and SYSREF) and we are operating at 5Gbps lane rate in 40X mode. FPGA is operating at 125Mhz device clock and ADC is also operating at 125MHz sampling clock(Genarting 500MHz from LMK since there is 1/4 buffer in path). We are creating 2 square waves from the square wave generated by FPGA using 1*2 splitter and one channel is being used as ADC input and other channel as reference for the scope to measure the total delay in the path.
We did testing with this setup and did some measurements but in every 5-6 power cycle we are getting is variation of 8ns which is eual to our device clock period. Our total latency in the path is around 789ns and some times it comes out to be 797ns. Intially we doubted that there might be some issue with the sysref capturing in the JESDRX side but we tried with multiple clock delay options in the sysref path in the LMK side for both FPGA and ADC. But the results are not improving, the total latency is changing but the 8ns variation is still coming. Then we analyze the captured results and I find out that the captured ADC MSB bit duty cycle is not constant always and it is taking some time to settle to 50% duty cycle. And when we are getting the 8ns variation the catured frequency is liitle change from the 6.25MHz, it is coming around 6.58MHz and if we calculate the period difference between the 6.58Mhz and 6.25MHz it comes out to be 8ns. So I am doubting this catured MSB bit frequency variation could be reason but not sure why this coming. So can you help us with this, is there anything we are missing from the ADC data capturing side. I have attached the captured results for your reference.
