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Tool/software:
Hi,
I am reaching out with a question regarding the timing specifications of the ADS7865 ADC, specifically about the "t2" parameter (BUSY rise delay) mentioned on page 7 of the datasheet in "Figure 1. Interface Timing Diagram."
The datasheet specifies a minimum value for t2 as 3 ns, but the maximum value is not listed. Could you please confirm the maximum value for t2?
To provide some background, we are designing an FPGA to interface with the ADS7865 to retrieve ADC values. Our current design reads data from the ADC after a specific delay following the CONVST output. Since t4 specifies the timing from the rising edge of BUSY to the falling edge of RD, we need to confirm whether the current design satisfies t4 even in the case of the maximum delay of t2.
Thanks,
Conor
Hello Conor,
Thank you for your question!
the max value for T2 depends on multiple variables and it is not as limiting as the minimum spec. One of the most critical variables is the CONVST command timing, explained in Figure 2 under the timing table.
It explains how the region that the CONVST command happens dictates on which rising cycle the conversion will begin (when staying withing the designated known regions; 10ns before or 5ns after the rising edge of the clock cycle). Since the Busy signal signifies the conversion time, the delay between CONVST and Busy should be somewhere between 3ns to about where its corresponding rising clock edge is, which also could vary depending on the clock speed.
If there a way to define the specific delay to the CONVST toggle point related to the clock that would probably make it easier. Or if there is a way to make the CONVST toggle point position repeatable , that too.
Best regards,
Yolanda
