Other Parts Discussed in Thread: LMK04828, LMK04826
Tool/software:
Hi,
We are planning to prove multi ADC synchronization with our JESD IP. The current setup includes two AFE58JD48EVM board, one LMK4828 eval board and one EFINIX titanium FPGA eval board. I have attached the setup diagram for reference.
- We are planning to use an external LMK04828 / LMK04826 Evaluation board as it can generate required phase aligned clocks and sysrefs for the secondary LMKs.
- Divider reseting will be used to generate synchronized device clock and sysref for secondary LMKs.
- Sysref: Continuous/ Pulsed Sysref will be generated from primary LMK. (For 5 Gbps, Sysref frequency = 3.90625).
- Seconaday LMK will be operating in ZDM mode to generate synchronized device/sampling clock and sysref.
- Secondary LMK will not generate any sysref. It will just forward the incoming sync signal to the Sysref Path. Since there is D Flipflop in the path. External sync from primary LMK is phase aligned with the VCO of the secondary LMK before forwarding to the output
- We will be using two FMC male to female cable to connect both the ADC EVM to single EFINIX eval board.
- There will be two seprate JESD204B RX IP in EFINIX eval board and the captured data from both the JESD RX IP will be captured in the BRAM and then will be checked on wavevision.
So before proceding we want to confirm whether the current testing scheme is feasible and we are thinking in right detection.
Can test the multidac synchronization with this setup ?
Please let us know if we are missing something.
