AFE58JD48EVM: Query regarding the Equalization capabilites of AFE58JDEVM

Hi,

You can check SEL_EMP_LANE in datasheet to do this .

Are you using custom capture card ? Do you see this issue at lower speed ?

Hi Sachin 

Thanks for the info, we tried adding equalization on the path but didn't worked out, we are still getting disparity error. 

Yes we are using a custom card, at 5gbps we didn't get this type of issue. 

For 12.5GBPS lane supported only for short trace length . What is your trace length ? 

Can you try increasing supply voltage by 50-100mV and check ?

Hi Sachin 

Thanks for the response! 

Which supply voltage need to be increased  DVDD_1P15 ? 

or you are asking to increase the voltage swing ? 

Is there any option in the IC to increase the CML voltage swing ?

Yes you can try increasing DVDD_1P15  supply and FPGA Supply also . 

There is no option to increase CML swing.

Hi Sachin 

Thanks for the response ! 

I tried to increase the DVDD_1V15 to 1V25 and change the presets also, but still I am getting the same issue. Getting disparity and symbol error on the lane. 

I tried two more test : 
1. Generating an internal sine wave samples before transport layer, with those sine wave samples the link is clean with zero disparity errror. 

2. Tried PRBS23 samples option on the ADC to send PRBS23 data on the link, with that I am getting disparity error and symbol error on the lane. 

Hi,

How does your eye diagram is looking ? Did you check that ? 

Also what is the lane length ? What is the material used in PCB ? Have you taken care of material selection in PCB? High speed lanes needs special PCB material .

Hi,

Since this is  NDA restricted part , we would like to discuss this over email . Please reach out to ultrasound_rx-support@list.ti.com