• State Resolved
  • Locked Locked
  • Replies 5 replies
  • Subscribers 46 subscribers
  • Views 338 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADS54J60: Issue interfacing ads54j60 with jesd204c ti ip core

Karthik BN
Prodigy 30 points
Part Number: ADS54J60
Other Parts Discussed in Thread: LMK04828,

Tool/software:

We are using ADS54J60 ADC IC and LMK04828 IC. The register configured are mentioned in the attached file. The rx_samples_valid signal is not going high. I am using 4244 ADC Mode with no decimation. I have observed that the pull-up voltage in INAP, INAM, INBP, and INBM are 2.8V initially and after hardware reset its 2.6V is there any problem in such case.

The schematic and the changes in the IP core is given in the attached file. Please let me know if any changes are needed.ADC_Query.docx

Thank You,

  • 0
    TI__Mastermind 41940 points

    Hi Karthik,

    Yes, the INA and INB pins should be a DC common mode voltage of 2.0V.

    Are you sure nothing else is going on here?

    What is the voltage of the VCM pin?

    Regards,

    Rob

  • 0 in reply to Rob Reeder
    Prodigy 30 points

    Hi Sir,

    The voltage I am measuring in VCM is 2.9V.

    Will this cause an issue because in the jesd204c TI IP Core the rx_pll_locked value is 3, and rx_all_lanes_locked is 1. But rx_sample_valid is 0 and sample data is all 0's.

    Thank You,

    Karthik

  • 0 in reply to Rob Reeder
    Prodigy 30 points

    After replacing the ADC IC now VCM is 2.1V, INA and INB are 2.0V. But the rx_sample_valid is 0 and the data is all 0's.

  • 0 in reply to Rob Reeder
    Prodigy 30 points

    Hi Rob Reeder,

    Please find the attached customized board schematic and pin mapping block diagram. 

    Tried to reduce the data rate and check

    4.9Gbps:        adc_clk     = 491MHz

                          Sysref        = 1.9MHz

                        Rx_sys_clk = 122.88Mhz

                        MGT_clk    = 122.88MHz

     2.5Gbps:        adc_clk     = 245MHz

                          Sysref        = 0.97MHz

                        Rx_sys_clk = 122.88Mhz Custmize Fast ADC Board Schimatic.pdf

                        MGT_clk    = 122.88MHz 

    Still we are unable to get the data from ADC.

     

    set_property PACKAGE_PIN AE8 [get_ports {xcvr_rx_p[0]}]

    set_property PACKAGE_PIN AG8 [get_ports {xcvr_rx_p[1]}]

    set_property PACKAGE_PIN AJ8 [get_ports {xcvr_rx_p[2]}]

    set_property PACKAGE_PIN AH10 [get_ports {xcvr_rx_p[3]}]

     

    Thank You,

    Karthik B N

  • +1 in reply to Karthik BN
    TI__Mastermind 41940 points

    Hi Karthik,

    Please look at the incoming data when SYNCb is asserted (driven to 0 from the FPGA) and confirm that you see the data change from all 0’s on the data lanes to all 0xBCBC, this will confirm the ADC is going into CGS and ILAS correctly.

    You can also check that when all lanes have achieved 0xBCBC for long enough time (4 frames of continuous 0xBCBC, I believe) that the FPGA drives the SYNCb signal HIGH to let the ADC know it has received the data and knows the lane skew, and is ready to start receiving actual ADC sample data, at which point the ADC changes to standard output data rather than 0xBCBC.

     If the converter does 0xBCBC as expected and then continues to send all 0’s, I would suspect ADC config is wrong. If it sends seemingly correct sample data and then changes to 0xBCBC again or all 0’s after some time, then I would think ADC digital power supply is insufficient, or FPGA configuration is not correct.

    I don’t know anything about the Xilinx provided jesd ip configuration. I may have to loop someone else in to help provide guidance.

    Thanks,

    Rob