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ADC3683EVM: TSW1418EVM, TSWDC155EVM, external vs. onboard clocking

K
Prodigy 10 points
Part Number: ADC3683EVM
Other Parts Discussed in Thread: TSW1418EVM, TSWDC155EVM, ADC3683

Tool/software:

Good Morning,

My questions are in regards to the ADC3683EVM and the TSW1418EVM, which are two devices I currently have. I am trying to set up a test using the guide in Question 1 below. We currently have only one signal generator and are exploring the onboard clocking option, but I want to make sure that it's worth it to go through the effort of modifying the board first.

I've also been advised to procure a TSWDC1455EVM, but if nothing significant changes between the two boards (particularly with respect to clocking) I don't see the point?

Forum posts I've browsed/referenced:

https://e2e.ti.com/support/data-converters-group/data-converters/f/data-converters-forum/1468729/adc3683evm-an-issue-with-complex-decimation-when-using-the-internal-clock-cdc-and-tsw1418

https://e2e.ti.com/support/data-converters-group/data-converters/f/data-converters-forum/1416020/adc3683evm-is-it-supported-by-tswdc155evm/5642545?tisearch=e2e-sitesearch&keymatch=TSW1418EVM#5642545

  1. External vs. Onboard clocking
    1. Confirming 65MHz and 292.5MHz for external clocking? Can other values/the same value be used? I found these on a forum post.
    2. Question 1: If we upgrade to the TSWDC155EVM, is the guide below still valid? Particularly with respect to external vs on board clocking but also in general
      1. https://www.ti.com/lit/ug/sbau360/sbau360.pdf?ts=1741798491300&ref_url=https%253A%252F%252Fwww.bing.com%252F
    3. Question 2: General clocking question — would it be acceptable to use a single signal generator that can generate multiple RF signals?
    4.  
  • 0
    TI__Mastermind 38690 points

    Hi K,

    I apologize for the confusion on the data capture boards. We are in-between data capture solutions as we have had a few FPGAs go obsolete on us and we were no longer able to get the board assembled.

    Please use the TSWDC155EVM for the ADC3683EVM. The TSW1418EVM is no longer supported. I will contact you offline to help with this matter more.

    To address your clocking questions. Please use external clocking. The current EVM does not support all clocking modes and frequencies. We are currently redesigning these EVMs as well to help remove confusion.

    Please use external signal generators for RF signals as well.

    Regards,

    Rob

  • 0 in reply to Rob Reeder
    TI__Intellectual 1300 points

    Hello,

    To answer your questions:

    1a. We only support external clocking for the ADC3683EVM. Assuming you are clocking the EVM externally, you can use any sample frequency within the specs of the ADC3683 (0.5 to 65MHz). The corresponding DCLK can be determined using the following formula found in the datasheet, based on your sample frequency and operational mode:

    Bypass/Real Decimation:

    DCLK Freq = (Sample CLK Freq * Resolution / # Wires / Decimation Factor) / 2

    Complex Decimation:

    DCLK Freq = (Sample CLK Freq * 2 * Resolution / # Wires / Decimation Factor) / 2

    1b. No, we will send you a new software package and new user's guide with the TSWDC155EVM

    1c. Yes, using a single signal generator with multiple output channels is okay.

    Best,

    Luke Allen

  • 0 in reply to Luke Allen
    Prodigy 10 points

    Thank you!

    Looking through the guide, I see the warning to ensure both external clocks are "frequency locked." Is this referring to the external 10MHz reference that they should both be connected to?

    Also just to verify since I couldn't find anything about it in the guide -- are there certain parameters for the clock signals besides frequency and power? I'm assuming a 50% duration square wave., and I was looking at the onboard clocking for pulse parameters:

    CDCI6214 Ultra-Low Power Clock Generator With PCIe Support, Four Programmable Outputs and EEPROM datasheet (Rev. F)

    Page 11 table 6.22 of the guide above has the pulse characteristics of the onboard clock, are these what the external clocks should follow?

  • 0 in reply to K
    TI__Mastermind 23760 points

    K,

    Yes, the sample and DCLK need to be reference locked by the 10MHz or other methods, otherwise the sample clock and data clock will drift apart over time. The clock can be sine or square wave.