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TSW12QJ1600EVM: Configuring ADC with TSW12QJ1600EVM

Panagiotis Gkountoumis
Prodigy 20 points
Part Number: TSW12QJ1600EVM
Other Parts Discussed in Thread: ADC12QJ1600

Tool/software:

Dear TI team,

I am using a TSW14J58EVM and TSW14J58 boards to implement the JESD204C protocol with the TI JESD240 IP. I used the ADC12QJxx00 GUI (Version 1.2 from 30 March 2021) to program the ADC (ON board oscillator, Fs=1000 Msps, JMODE8) but the TRIGOUT Clock Output is not stable (varies from 70-79 MHz and not 386.71875MHz that I was expecting for RX_DIV=32) and FPGA MGT QPLL never locks. Checking the ADC pll on the GUI is not locked either (V=3, P=4, N=20) and the RX_DIV is fixed at 64.

Because of this issue: https://e2e.ti.com/support/data-converters-group/data-converters/f/data-converters-forum/1354764/tsw14j58evm-tsw12qj1600evm-interfacing-with-tsw14j58evm-having-a-issue-with-capturing-the-data

I tried also the python script. I modified it to get the SN and the output looks like this:

***************************************************************************
        Initializing ADC12QJ1600 instance with defined attributes
        Got Init Bit
        ADC device initialization complete successfuly
        ADC is ready for programming
***************************************************************************

***************************************************************************
        Initializing ADC12QJ1600 instance with defined attributes
        Got Init Bit
        ADC device initialization complete successfuly
        ADC is ready for programming
***************************************************************************

P = 2, V = 4, N = 20, FVCO = 8000000000.0
Setting the ADC's JMODE to 8

P = 2, V = 4, N = 20, FVCO = 8000000000.0
Setting the ADC's JMODE to 8
Done

But I don't see any change to the TRIGOUT Clock Output frequency. I don't even know if the script works since I tried to do some single register reads and always returns 255.

I noticed also that on the carrier board the PLLREFO clock is not routed at all. In this case I have to use the on-board oscillator to generate the free_running (125 MHz) and system clocks (12.375/33= 375 MHz for line rate of 12.375 Gbps, 64b/66b and line rate of 32 bits) according to the 6.4.7 of the TI204C-IP JESD FPGA IP User Guide.

Could you please help me with this?

Thank you in advance,

Panos

  • 0
    TI__Expert 6150 points

    Hello Panos,

    Can you please check jumper J19 on the board. It looks like the SPI through the FTDI chip is not working. This board has the option to be programmed through the USB or over the FMC and this jumper controls a mux that selects where the SPI lines come from. For USB control it should be uninstalled.

    Thanks,

    Eric 

  • +1 in reply to Eric Kleckner
    Prodigy 20 points

    Dear Eric,


    thank you for the reply. The problem was the port on the python script (I think it was C by default). I can see now a stable TRIGOUT Clock Output frequency at 193.359375. Could you please comment on the correct sys_clock frequency on the IP core? The sys_ref is 520.832 KHz on my case.

    Regards,

    Panos

  • +1 in reply to Panagiotis Gkountoumis
    TI__Expert 6150 points

    Hi Panos,

    There are two clocks you need the Trascevier reference clock and a application layer clock. 

    The SYS Clock has to follow the equation LR/66 (for 64b66b modes) or LR/80 (for 8b10b modes) where LR is the line rate of the link

    The XCVR reference clock requirements are much more relaxed and can be most integer divisors of the LR, for convenience we typically let the XCVR reference clock equal the SYS clock.

    Thanks,

    Eric