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Original question:

TI-JESD204-IP: How to package TI204C-IP as IP that can be used outside reference design

TI-JESD204-IP: VHDL Wrapper for TI-JESD204 IP

ILIAS ALEXOPOULOS
Prodigy 60 points
Part Number: TI-JESD204-IP

Tool/software:

Hello,

I am trying to integrate the JESD204 core into my design. As my primary language for the design is VHDL I tried to create a wrapper around the IP.

I am using VIVADO 2022.2, as I am constrained by other IPs of the design.

After failing to make the system work, I replicated the example provided and started using VHDL from the top layers up to the TI_204c_IP_Ref block. This works.

See the picture below on the design hierarchy:

The simulation logs show the following setup:

I need to separate the TI JESD204 IP and have it as an independent block to help me with integration and verification. So I created a VHDL wrapper, that use a SystemVerilog Wrapper which instantiates the SVP file alone. I moved the rest of the Reference code functionality to external VHDL modules. 

I used the intermediate  SystemVerilog Wrapper just as a precaution of not changing language domain on the encrypted IP.

The simulation hierarchy is as follows (note that I am using VHDL-2008 in this case)

The problem is that although the first design simulates correctly, the second one with the wrapper does not.

Seems that all the output signals of the IP are 'U', 'Z' or 'X'. I tried to use the MGT_GPIO signals from the GTH wrapper to send them to the top layer and observe if the signals reach the top level, but this also does not work as the signals continue to be in the 'U' state. Example signals that are undefined or tri-stated are the Q/CPLL Lock signals for example (but seems all outputs are in the same such state).

It seems to me that the IP is not connected for some reason. Simulation also starts a lot faster in this failing case.

I also did the same architecture with a small test block to do the same wrapping methodology for a sample System Verilog, and the I/O seems to work as expected.

Please see also that in the failing design VIVADO hierarchy the second layer and below of the hidden nodes (including the GTH driver) are grayed out. Although I can modify the GTH, there seems to be something different. VIVADO does not complain about anything.

The wrappers also pass the constants (through Generics) from VHDL to SV.

Can you provide any insights of what could be wrong, or if I must use a different approach?

Thanks in advance,

Ilias

  • 0
    TI__Intellectual 2260 points

    Hi Ilias,

    I notice that you have added the entity file of the TI IP to the sources list. Please let me know there is a specific reason for that. The entity file is purely intended to be a reference and should not be included in the tool flow (this is mentioned in the user guide).

    Apart from this, I wasn't able to see anything obvious in terms of an error. While we internatlly don't use this, we have a number of customers who have a VHDL based top level flow, and they create a wrapper around the core file to pass the parameters and integrate the IP.

    Regards,
    Ameet

  • 0 in reply to Ameet Bagwe
    Prodigy 60 points

    Dear Ameet,

    I apologize for my late reply, but I was in business trips the last couple of weeks.


    I figured out the problem to be a passing parameter issue with strings between VHDL and SV. I kept the majority of parameters in a verilog header, like the IP_PROTOCOL (this was one of the culprits) and other parameters with strings (like "NORM", "NO" etc). I left in the VHDL generics only bus length  related parameters that affected the interface. This created a cleaner method to control the JESD204 core using mostly the verilog header for the JESD204 parameters and leaving the interface-related generics to control the I/O sizes.

    The second issue I had was related to a mistake in my testbench, where the IP was working but the GTH transceiver was not synchronizing. It turned out that I used a wrong clock frequency and thus the PLL could not synchronize. These actions resolved all the problems and the setup worked correctly.

    Thank you for your support.