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TI-JESD204-IP: Getting to link up / PRBS testing with ADC09QJ1300 via the TI provided JESD IP

Aiden Morrison
Prodigy 65 points
Part Number: TI-JESD204-IP
Other Parts Discussed in Thread: ADC09QJ1300,

Tool/software:

Hello all,

I'm working on my first JESD204 based design which incorporates a TI ADC (ADC09QJ1300) on a custom FMC board and I am trying to make use of the TI-JESD204-IP to get to link up, and validate with one of the PRBS sequences.

I've brought up the supply voltages, clocks, frequency generators (sampling clocks, and sysref for both the ADC and FPGA generated via a Si5386 jitter attenuator with JESD support) and I'm able to talk with the ADC via SPI (ID register coming back with expected values etc) so everything is looking good on the hardware side, but on the software side my inexperience is biting me.

In trying to make use of the TI-JESD204-IP, I've run into a few problems that I'm hoping people here can guide me through:

1) Past posts here from 2023 such as this one (https://e2e.ti.com/support/data-converters-group/data-converters/f/data-converters-forum/1299136/ti-jesd204-ip-how-to-use-ti-204c-ip-on-vivado-block-design) indicate that the TI-JESD204-IP gained vivado block design support in 2024, but there's nothing in the documentation pdf included in the IP (dated 2021) about using this as one would with e.g. the ADI IP block.  Does the IP actually support this methodology?

2) The website for the TI-JESD204-IP says "TI will assist the user in the configuration of the initial link, customized for use between the specific FPGA platform and TI data converter JMODE. TI will provide the IP via a secure download link after it is tested and ready for deployment." while the documentation file included says in step 3 of the usage instructions "You will be provided a reference design that is customized for your application needs and targeted for a Xilinx development kit or a prototype FPGA boad." Yet outreach to TI about following their instructions has resulted in no feedback in 2 weeks.

I am trying to pursue this offer they give in multiple places as the four provided examples seem to target a specific loopback board rather than a specific DAC or ADC, but the documentation is light on the details of how to go about reducing the examples to be TX or RX only. 

Could anyone here share contact info of their PoC that has responded when asked to follow the TI specified process? I've seen Mr. Ameet around here who appears to be the author of the 2021 documentation but the forum doesn't allow to directly message.

3) I know it's a long shot, but if anyone has a vivado block design project that implements a single ADC receiver using the TI-JESD204-IP that they are able to share, please let me know.

  • 0
    TI__Intellectual 2260 points

    Hi Aiden,

    The TI IP version with automated block design support was ultimately not released because most customers have preferred doing this on their own. Adding a verilog wrapper over the top level makes it block design compliant (or it can be packaged through the IP packager). 

    The TI IP does not support IBERT testing, because Xilinx offers reference designs that handle it. If you would like to implement a link for the Ultrascale+ class of devices, our recommendation is to use the VCU118 reference design as a starting point. This can then be edited through the IP parameters for the targeted LMFS mode (along with the transceiver configuration). The final step will be to modify the refdesign_rx.sv file to map the lane data to samples. 

    Kindly let me know if this addresses your queries. 

    Regards,

    Ameet

  • 0 in reply to Ameet Bagwe
    Prodigy 65 points

    Hi Ameet,

    Nice to meet the author of the IP, and thanks for taking the time to reply.

    It does answer my question about point 1 regarding the decision to not implement the block design support. 

    Additionally, thank you for mentioning the IBERT module as that seems to be the perfect tool for me to validate the link level of the design in conjunction with the pattern generators built into the ADC09QJ1300. I will pursue this.

    Regarding the recommendation to use the VCU118 example as a starting point, this seems contrary to the clear language on the IP page and in the IP documentation that TI will produce an example capable of getting to link up with my custom FPGA board, so could you please recommend someone to get in touch with at TI to do so? I have to insist that TI follow through on their advertised support service as otherwise it throws into doubt the reliability of all TI representations about their products.

    Thank you in advance.

    Edit: I have sent a friend request, Ameet. I would like to discuss an idea for how some small updates could be made to the documentation that would both enhance the TI-JESD204-IP, and allow TI to live up to its statements.