Tool/software:
Hi DDC232 team
We are developing DDC232CK board. The conditions are shown below.
Non continuous mode, 20bit output,12.5pC
CLK: 10MHz, DCLK: 20MHz
We have an offset fluctuation problem. Attached file shows the fluctuation.
Our board can output dark offset with about 20 standard deviations in Continuous mode. However, the deviation becomes larger in Non continuous mode.
After analyzing the cause, we found that the offset fluctuation behavior changes when the phase between CLK and DCLK is shifted.
The data sheet instructs that the phases of CLK and CONV should be aligned but does not specify the relationship between CLK and DCLK.
Are there any recommendations regarding the relationship of these clocks to reduce the fluctuation?
We also confirmed that the fluctuation becomes larger when the phase of CLK and CONV is shifted.
Thanks