ADC3669EVM: Operating mode of the ADC3669 converter

Hello,

Can you please clarify what you mean by variable clock?

Best,

Luke Allen

During data acquisition on CLKP/M, a variable‑frequency clock—operating in the so‑called SWEEP mode—will be supplied in the range of 150 MHz to 400 MHz.

Hello,

The only issue I see here is on the FPGA side. If you can get your FPGA capture to change rates when your clock frequency changes rates, I believe this should work. However, I am reaching out to the design team to verify that this is possible from the ADC side.

One more question to clarify: are you wanting to sweep the sample clk frequency in gradual steps, such as 150MHz, 155MHz, 160MHz, etc., or are you wanting to jump to different sample frequencies within your 150MHz to 400MHz range, such as 150MHz, 350MHz, 200MHz, etc.?

Best,

Luke Allen

Hello,

Okay, in that case I’ll wait for feedback from the project department, and the frequency will be adjusted gradually.

Hi Robert,

I have recieved word from the design team that this is possible, however you will need to freeze some of the internal background loops before the sample frequency change and unfreeze them afterwards. If this is of interest, I can provide you with the register writes.

Best,

Luke Allen

Hello,

OK, can you give me the registers?

But does that mean that every time the sampling frequency changes, the register needs to be changed as well?