ADS8568: recommended MCUs?

Part Number: ADS8568

Tool/software:

Hey everyone,

I'm coming from the stm32 ecosystem and the issue i have is that interfacing with the ads8568 I'll only be able to run a single data line SPI of around 45Mhz and with the high end H7 series I can hit 100 Mhz.

For my application I am running three ADS8568 in a daisy chain and even running an fpga/cpld i'll still be limited by the spi line.

In addition I want to store the data in an sd card and then push it to the cloud via a lte module.

I assume that to run the max data rate I'll need to interface with only an fpga.

Whats the max sample rate that can be achieved interfacing the ADS8568 with a MCU and would SPI be the recommended communication method?

Thanks in advance 

  • Hello Pieter! 

    Welcome back to TI's E2E forum! 

    For my understanding, you are using 3x ADS8568 in daisy chain and are looking for an MCU that could enable maximum data rate for the ADS8568? 

    Currently you are using an STM32H7 that can go up to 100MHz, but find the ADS8568's  45MHz SCLK max limiting?

    Is a total of 24 single-ended, simultaneous sampling, 16-bit ADC what is needed? Any front end requirements? Would a device like the ADS9813 be of any interest?    

    What is the sample rate and data through put goal? 

    The ADS8568 has an max sample rate of 650ksps when used in Parallel mode, and 480ksps in Serial Mode. The interface that supports the daisy-chain feature is the serial interface. 

    We have this user guide that briefly explains timing considerations for this device family when using TMS320 DSPs from TI.

    For the MCU selection, data storage in SD card, and cloud/ITE modules I would recommend asking in one of MCU/DSP forums. 

    Best regards, 

    Yolanda

  • Hi Yolanda,

    Thank you so much for the prompt response and apologies, i think my prior post was a bit of a ramble.

    I'm currently using a stm32 and I do not mind the 45Mhz sclk.

    This is more a question of how can you run this ADC at max data rate other than using a FPGA/CPLD?

    I havent seen any MCUs that can take advantage of the QSPI interface that this has nor the parallel interface.

    I can see there is a C2000 range from TI that has an integrated CLB which might be usable to to configure a custom peripheral and be able to have the mcu directly access it or maybe a DSP like the TMS320 with a parallel interface is the recommended interface.

    Sadly I havent been able to access the user guide you linked.

    If this is better suited to another forum i'll move it there.

    Thank you for the help and apologies again for the ramble.

  • Hello Pieter,

    No need to apologize, I just wanted to make sure I understood. Thank you for explaining again.  Also, I do apologize that the link did not work, I have added it again:

    ADS8528, ADS8548, and ADS8568 Timing Considerations

    In case it does not work again, it can be found in the ADS8568 product page, under Technical Documentation

    That application note highlights some vital timing that is necessary to achieve the fastest throughput. What it comes down to is having a controller that can provide an external clock and that it is synchronized to the CONVST in the nano seconds range.  

    A critical timing with this device is the alignment of the conversion clock and the CONVST signals to ensure that the device takes 19 clock cycles to convert instead of 20. Then having the minimum delay possible to start reading the output data.

    From the document it does seem like the Cx000 family could be used to get to or close to the maximum throughput. They might not have an explicit QSPI functionality, but configuring for a QSPI could be possible with some additional configuration, like you mentioned. I believe this E2E thread was eluding to something related to this functionality.

    Also, just in case it its of interest, the Sitara MCUs (AM243x, AM64x, AM273x...) have QSPI and/or OSPI or some FSS. 

    I would suggest asking in either the C2000s or Sitara forums to find an MCU solution. Unfortunately I don't currently have an MCU solution, my apologies. 

    Best regards, 

    Yolanda  

  • Thank you Yolanda, I appreciate the detailed and well written responses you always provide.

    I will check in with the C2000 forum to see if they have any additional MCU recommendations

  • Hi  ,

    Apologies, I have a quick follow up question which I didn't think about until now.

    As the max sampling rate of the ads8568 is 400ksps, I assumed that if I daisy chained 3 then the sampling rate would decrease to 400/3 = ~133 ksps.

    Given that the ADS8568 sclk input can operate at a frequency of 45 MHz would it then be possible to have 3 ADCs daisy chained running at ~400 ksps?

    Given a sclk requirement of  (16 bits x 24 channels x 400 000 samples) / 4 data lines = ~38.4 MHz (ignoring conversion time, etc).

  • Hello Pieter, 

    No need to apologize, that's what we are here for! 

    400ksps would be the max sample rate when reading from only 1 device, so when reading from 3 devices the sampling speed will decrease. 

    Similar to Figure 41 in the datasheet, with 3 devices in daisy chain, using all 4 SDOs, it would take 32 SCLKs per SDO per device in daisy chain to get all 24 channel data, that plus the time to convert, lets use 1.7us since its the max spec (this could be decreased a bit if polling the busy signal), plus the las tFSCV 

    Meaning t_sample ~= t_conv + (32*SCLK*Daisy-Chain Devices) + tFSCV

    --> t_sample = 1.7us + (32*22.22ns*3) + 40ns =~ 3.87us --> 258ksps

    Best regards, 

    Yolanda