Other Parts Discussed in Thread: ADC12J4000
Tool/software:
Hello everyone,
I’m using ADC12J4000EVM with KCU105 board and I’m trying to receive data without using JESD204 IP core in FPGA. I’ve aligned bytes and lanes, so RAMP TEST, ILA TEST and D21.5 TEST works fine. Now I need to split data into 12bit samples and place them in the correct order. I set up ADC as if I’m going to capture data using HSDC PRO, than I turn off scrambling by writing 0 in bit 7 in addr 0x201. So, I use Bypass Mode, No Decination, DDR = 1, P54 = 0; LMF = 8,8,8 and scrambling is turned off (bit 7 in addr 0x201 is zero). I expected to see frames described in tables 12 and 13 in ADC12J4000 datasheet, but I see no tail bits (they must be zero according to ADC12J400 datasheet). Also when I turn on test pattern mode (write 1 to bit 2 in addr 0x58) I don’t see ADC Test Pattern symbols on lanes, as is described in Table 33 in ADC12J4000 datasheet. I know that there is swapped polarity on D[7...0] connections, so I use «rxpolarity» port in FPGA transceivers and connect it to 1. I tried to connect it to 0, but I can’t see tail bits either as 00 or FF.
Obviously I do something wrong. How can I get TPM data from ADC and how to see tail bits in data stream? I would be very grateful for any help in solving this problem.
Best regards, Hannah.
