AFE5832: LVDS data alignment state changes when adc mode switchs from test mode to normal mode

Tool/software:

Hello,

        Now I'm using AFE5832LP and FPGA to support my work,But I'm encountering a LVDS decode problem.

First I set the afe5832 in test mode to make an eye pattern scan, in order to get the best delay for every channel.And then I switch the mode from test mode to normal mode ,but i find that the data alignment state turns bad.

It seems like that bits order changes.Why does it happend? What should I do to solve this problem?

Thanks.