Other Parts Discussed in Thread: AFE7900
Tool/software:
We are currently in the process of integrating Xilinx’s ZCU102 evaluation board with TI’s AFE7900 EVM, with a particular focus on SPI communication. I would appreciate your guidance on a few aspects of this integration.
We have to generate a waveform from 0.8GHz to 2.8GHz with AFE 7900 (DAC 12GSPS rate) with step of 100MHz with 10usec step duration. Means 0.8, 0.9, 1, 1.1 etc every 20usec 100MHz varies and it repeats. So, we would like to use 16 NCO Frequency Profile configuration which was there in AFE7900. As per the datasheet frequency switching speed mentioned is 15usec hence we should get 20usec easily.
While SPI is straightforward and relatively easy to implement, this approach requires hardware modifications such as desoldering and resoldering resistors, which is not ideal. A software-based switch would have been more convenient. If SPI is the recommended path, could you kindly provide:
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Complete board bring-up procedure
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NCO profile configuration steps
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Timing configuration commands along with the corresponding timing diagrams
Additionally, if this configuration can be implemented through RTL, we would highly appreciate your guidance. Otherwise, if it is only possible through the PS, please advise on how we can achieve frequency changes at a 20 µs rate.
Your support on these aspects will be very helpful for our integration efforts.
We found few issues while implementing SPI:
We are facing some challenges while implementing SPI for the integration of the ZCU102 evaluation board with the AFE7900 EVM. Specifically, we encountered errors with the reference SPI controller design provided by TI, which failed to synthesize. Could you please assist us in resolving these issues and help establish proper SPI-based integration between the ZCU102 and the AFE7900 EVM?
In addition, we would appreciate your guidance on the following points:
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What is the recommended method to configure 16 NCOs on the AFE7900 EVM?
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Once SPI functionality is properly established, how can we configure the AFE7900 EVM through SPI writes?
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What is the maximum speed at which SPI commands can be transmitted via the ZCU102’s Processing System (PS) and Programmable Logic (PL)?
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Would it be feasible to modify the JESD reference design by incorporating the SPI design, generating the .xsa file, and operating it from Xilinx Vitis?
As of now we implemented SPI Driver in RTL and verified in ILA & on Hardware probe. Now our target is to board bring up & 16 NCO profile configurations.
Looking forward to your response.
