Hello
I'm tring to run a TI-JESD204C-IP loopback simulation on Vivado(Reference Design: zcu102_64b66b).
I run the simulation following the steps outlined in the post below.
TI-JESD204-IP: Simulation of loopback design in Vivado - Data converters forum - Data converters - TI E2E support forums
The user guide states that “rx_lane_data_valid asserts exactly after two cycles,” but in this simulation, it asserts after one cycle. Is this correct behavior?
-
Ask a related question
What is a related question?A related question is a question created from another question. When the related question is created, it will be automatically linked to the original question.