ADC3910D025: Digital data seem noisy even with shorted inputs

Hi Mohammad,

Please send over some output digital data plots so we can best determine what is the issue.

If you have a schematic or setup to send over that would help as well.

Regards,

Rob

Hi Rob,

Here are some results from the inputs shorted to VCM. 

The data was collected at 1 MSPS, they contain some frequency component at ~400kHz. But that number could be folded from another freq. The inputs look very stable on the oscilloscope.

This sounds like very similar to the previous problem in the old forum. 

We ran some further experiments, this time with 100 Ohm in series with the analog input. Vref is also shorted to ground.  The results look much better, but still not as good as we would expect. 

Any thoughts on this?

Hi Rob, Any update on this?

Hi Mohammad,

The min sampling rate is 5MHz, if sampling at 1MHz, then the ADC won't work.

Please do not ground the VREF either, VREF should be 1.2V.

Your schematic is difficult to follow, please send over a clean version if you want us to help troubleshoot more effectively.

Regards,

Rob

Hi Rob,

Thanks for following up. We will run it at higher sample rate and update you. 

As for Vref, the datasheet says it should be either supplied externally, or it should be grounded (Page 3). If we use the internal Vref (default) should we grounded as the datasheet says, or do you think it should be bypassed?

The schematic is simple, at the moment, the ADC is connected to a logic analyzer, and that's it. The sample rate and reset are applied externally, and the data is sampled using the logic analyzer. the two differential input are shorted to VCM. Still, we are seeing a significant variations on the data, as shown in the attached image previously. The datasheet (P. 20) shows that the data should be much more stable with a DC input (e.g., shorted inputs to Vcm). Any thoughts on this?

Hi Mohammad,

Might good to use our data capture card and SW to collect the data.

I assume this if your own board design with the ADC on it?

Typically, VREFs should not be grounded, but I will double check this.

Until you run the ADC at a higher sampling rate, I cannot comment, the ADC internally has timing closure for the sampling rates it is rated for.

If you violate that, then you should expect bad data collection.

Regards,

Rob

We'll update you with the higher sampling rate.

Yes, this is our hardware with the ADC3910, and we are trying to verify it. 

There seems to be a very similar problem in a thread that you were responding to, but it was taken private at the end, so I couldn't tell how it was resolved: "ADC3910 data has large mysterious signal, even when inputs shorted"

Could you please let us know how was that resolved?

Hi Mohammad,

The customer for that E2E post/thread had many issues, which we resolved. The customer ended up having to redesign the board.

Regards,

Rob

Hi Rob, 

We ran extensive tests today and here is what we found. 

- Everything below is 5 MSPS

- We programmed the ADC 3910 to generate a ramp test pattern to test the digital reading correctness. Everything looks OK for both channels:

- Next we tried to set it up to single-ended inputs, the two analog inputs are shorted to VCM, the results seem consistent and with low variations (good), for both channels. This is with offset binary:


and here is the histogram of the data: variation of within 5 counts:

-Next (the problem), using the exact same setup as above, we just changed the mode to differential. Both input voltages are still shorted to VCM. The variations are HUGE (~50)

Histogram:

The bottom line: There is a problem in the consistency of the data when we run the ADC in diff mode. Could you please look into that?

And here are the registers we wrote to:

Write(24, 0x000080)  // reset

//Write(24, 0x030B00) // differential
Write(24, 0x030B20)// single ended
Write(24, 0x008D40) // sets offset binary 

Write(24, 0x008920) 

Write(24, 0x008F10) // 

Write(24, 0x048402)

Write(24, 0x04BF03)

Write(24, 0x00A112) // ramp


Write(24, 0x00A240) // step size
Write(24, 0x00A300) // step size
Write(24, 0x00A480) // step size
Write(24, 0x00A500) // step size

Write(24, 0x00A600) // enable or disable test pattern

Hi Mohammad,

We will look into this, thanks for sending over the spi writes. This helps.

Regards,

Rob

Hi Mohammad,

Your SPI writes look correct to me. Something you can try is simply applying a software reset with no other writes. When the part is reset, it comes up in differential mode, twos compliment, no digital features enabled. This can help us understand if there is something on the board cauing this issue.

Best,

Luke Allen

Hi Luke,
Thanks for the confirmations.

We actually tried what you suggested, with soft and hard reset, and no other writes. The differential still looks jumpy. (sorry the data is not recorded)

Also, this applies to both channels A, and B

Hi Mohammad,

Thanks for confirming. Would you be able to share the full schematic and layout of your board so that we can take a look at it? We can take this offline into an email if you are more comfortable with that as well.

Best,

Luke Allen

Hi Luke, 

I can share KiCAD if that works. How can I share it confidentially?

Alternatively, I can share PDFs, but it still needs to be through a confidential channel.

Hi Mohammad,

Either one works. I'll close this post and we can move the conversation to an email.

Best,

Luke Allen