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Original question:

DAC61416: Frame Error Checking Time / from CS signal to ALMOUT signal

DAC61416: Use SDO only on a Read command

Hiromu Susami
Intellectual 1370 points

Part Number: DAC61416

Hi exparts,

The following is described in the CRC error check section of the DAC61416 data sheet.
"After the write command, a second access cycle can be issued to determine the error checking results (CRC-error bit) on the SDO pin."

  1. This means that the error check frame including CRC-error will be returned from the SDO pin when cs is lowered after the Write command?
  2. Is there a way to use SDO only on a the Read command?

The background to the above question is as follows.

  1. CRC check required to ensure data integrity -> Monitor with ALMOUT instead of SDO readback.
  2. Want to monitor Read command Ack to see the health of the DAC itself -> Enable SDO-EN for Read command.
  3. When SDO-EN is enabled, read back occurs during the Write command, and write cycles take twice as long as expected.

If there is a way to solve the problem of increasing the write cycle other than the above 2, please let me know.

Regards,
Hiromu

  • +1
    TI__Guru** 100725 points

    Susami-san,

    I don't think there is a way of reducing the number of communications to verify the error in a CRC. I think the best you can do would be to check the status register (0x02) for the CRC-ALM bit.

    This would involve enabling the CRC and the alarm, using the CRCALM-EN and the CRC-EN in the SPICONFIG register (bits 9 and 4 in register 0x03).

    When the alarm is triggered, read the status register at 0x02. This requires two communication frames, the first to tell the device you want to read from the register and then a NOP frame to clock out the data from the register. Once you determine the alarm comes from the CRC, then you would re-write the previous register write.

    Joseph Wu

  • 0 in reply to Joseph Wu
    TI__Intellectual 1370 points

    Hi Joseph,

    Thank you for your comment.

    Hiromu Susami said:
    "After the write command, a second access cycle can be issued to determine the error checking results (CRC-error bit) on the SDO pin."

    I want to confirm this point. Does it mean that while writing CH1 to CH16 continuously, SDO returns frames containing CRC error bits for the previous write access in parallel? Following figure shows my understanding for this CRC-error check.

    Regards,
    Hiromu

  • +1 in reply to Hiromu Susami
    TI__Expert 6390 points

    Hi Hiromu-san,

    Yes, you are right. Writing CH1 to CH16 continuously, SDO returns frames containing CRC error bits for the previous write access in parallel. 

    Thanks,
    Sanjay