ADS8681: For Source-Synchronous Internal Clock, how many bits of SDO could I obtained?

Hello Justin! 

Welcome to TI's E2E Forum!

There are two options for shortening the clocks needed in a data frame. 

1. Using a "Short" Data transfer frame. 
   1. The output data word is configured to include optional status flags after the conversion result --> output data = {Conversion Result D[31:16], Optional Status Flags D[15:2], 00b}
   2. In a short data frame, the clock counter can be less than 32, to enable only reading back data. Meaning that the data frame can be at least 16 clocks, 19 if some status flags are desired. 
   3. **Using this feature does invalidate the SDI command, appearing as a NOP command always.
      1. This is fine when reading back conversion data
      2. But when configuring to the device (reading or writing to the device register map) the data frame must be 32 bits. 
      3. Decrease the clock count until after configured and only conversion data will be read. 
2. Dual SDO
   1. This device has a feature where the multifunction pin (ALARM/SDO-1/GPO) can be configured as a 2nd SDO. 
   2. This cuts the data frame size by half, needing 16 clocks instead of 32. 

If status bits are required, for the full data and status bits (30 bits), then I would recommend using the dual SDO. Would this be an option for your design? 

Best regards,

Yolanda

Hi Yolanda, 

As currently my design is limited to single SDO, hence I would like to explore further into the first option.
As it seems that it is impossible to use source-synchronous internal clock method to obtain at least 20 bits, I would like to explore the option if I am using SCLK at 66.67MHz.

With SCLK, it seems that the t_DEN_CSRVS delay time could be avoided and allowed me to obtain data at my host controller merely after 10ns instead.

With this approach, it seems that it is possible for me to get 20 bits of data with very tight of timing constraint. 

Hello Justin, 

Thank you for the update, using an external SCLK with standard SPI does leave more room to extend the data frame.  If using the RVS as a trigger/interrupt could be an option, it could help increase reading time slightly to allow for a couple more bits to be read as well. 

Would you be able to share how the ADC is being used and what status bits are important to include in the read back for your system? 

Best regards, 

Yolanda

Hi Yolanda,

The current desired bits are the conversion data (16 bits), input alarm bits (2 bits) and parity bits (2 bits). 
The ADC will be connected to isolator(s) which then will connected to a main peripheral. Due to limitation of isolator (4 channels), I am only able to connect CS, SCLK, MOSI and MISO channel between the main peripheral and the ADC, which make connecting the RVS is less desirable. 

Thank you for sharing Justin, 

Then you are correct, using standard SPI with a controller sourced SCLK would be the ideal situation to get at least 20 bits for a 1MSPS throughput. 

As I'm sure its already known, but just in case, when configuring the device the data frame size must be 32 clocks, meaning the cycle time will have to be slower than 1MSPS during this time. 

Best regards, 

Yolanda

Out of curiosity, when I configure the device, would it be possible for me to use a shorter t_CONV, for instance 100ns instead of 665ns (since the SDO data is not going to be useful/valid during configuration), but using the same SCLK frequence (with 32 clock cycles)?

Hey Justin, 

Having digital transactions happening during the conversion is not recommended. Besides just affecting the sample being converted, there is a quiet time during the conversion cycle where it is critical to avoid digital transaction. Which is why it is recommended to wait until after the conversion is over. 

The multipurpose pin combining both CONVST and CS does make it more difficult to avoid this too. 

A solution aside the recommendation to wait until the conversion is over is also for the device to ignore CONVST/CS transactions once conversion has started. 

Is extending the cycle time during device configuration not an option? 

Would adding some "dummy" frames or delays between device configuration and data acquisition be permissible? If the full conversion delay was not needed. 

Best regards, 

Yolanda

Hi Yolanda,

I give it a thought on the using Standard SPI with host controller sourced SCLK, however I still unable to find a valid scenario where I able to get 20 bits for 1MSPS throughput. I hope you could help to provide more insight or correct my mistake in timing analysis (if there is any).

In my current draft design, my schematic would be based on Figure 7-25 from ADS8681 datasheet with isolation using ONE ISOW6441 model (currently, this is the isolator which I know that consist of DC-DC converter and have the best performance among the others).


My host controller has the internal clock running at 250MHz (4ns precision) which resulting in the t_CONV=668ns (instead of 665ns), t_(DEN_CSDO)=12ns (instead of 10.5ns) and t_(HT_CKDS)=8ns (instead of 7,5ns), and I did the timing analysis as below. 

1. With standard SPI, the SCLK is limited to 25MHz (by isolator). Hence, the full cycle will be
       t_cycle = t_CONV + t_(DEN_CSDO) + N∗t_SCLK + t_(HT_CKCS) = 668ns + 12ns + 20*40ns + 8ns = 1488ns (@672kbps)
2. With phased-delayed SPI, the SCLK is calculated via
       t_SCLK/2 - PWD/2 >= 0.45*t_SCLK ;  t_SCLK >=10*PWD
           As PWD worst case is 3ns, hence min(t_SCLK) is limited to 30ns (@33.33MHz).
       T_sclk >= 2*(t_(D_CKDO)+PWD+t_(trace+FPGA)+D_err)) >= 2*(12+3+1+0) >= 32ns (@31.25MHz)
           Assume trace+FPGA setup delay is really small (1ns), and the delayed mechanism could sync perfectly (0ns error)
       
       t_cycle = t_CONV + t_(DEN_CSDO) + N∗t_SCLK + t_(HT_CKCS) = 668ns + 12ns + 20*32ns + 8ns = 1328ns (@753kbps)
3. Source Synchronization with Internal Clock
       t_cycle = t_CONV + t_(DEN_CSRVS) + N*t_(CYC_RVS) = 668ns + 50ns + 20*15ns = 1018ns (@982.3kbps)

I unable to figure out a suitable SCLK (or how to implement it) which is capable to achieve 20 bits @1Mbps.

Hi Yolanda,

Thank you for your insight. I think it is allowed for my system to have longer cycle time during device configuration (but not for ADC data acquisition as the target is to achieve minimum of 20bits @1Mbsp). I will keep in mind that t_CONV is required to have at least 665ns when designing my design on my host controller. 

At the moment, the main issue is still with the technique on how to achieve 20bits @1Mbps with using only ONE isolator that is capable to perform DC-DC conversion (ISOW series).

Hello Justin, 

Your calculations are good. 

With standard SPI, the 1MSPS could be achieved for 20 bits with >60MHz SCLK. If there is a limit of 25MHz when using only one ISOW6441, then reaching 1MSPS would not be possible. 

Using the Source Synchronous with the internal clock would be the bet for highest throughput. As you showed, it is shy the 1MSPS by only 18ns. If possible with the FPGA, using the DATA_VAL[2:0] bits in the DATAOUT_CTL_REG register can be used to calibrate the data output. With calibration a more typical value of  tDEN_CSRVS can be used rather than a fixed max value. Depending on the system temperature conditions and expected ADC to FPGA path delays this calibrating the data out this way could save the 18ns needed for 1MSPS throughput. 

Best regards, 

Yolanda

Hi Yolanda,

Sorry that I failed to understand on how setting the DATA_VAL[2:0] would help with adjusting the t_DEN_CSRVS into a typical value. Based on the datasheet, the DATA_VAL[2:0] must set to 0XX in order to receive conversion data, setting it to other value will resulting in other designated pattern which make the ADC does not carry out its function. 

Could you help to elaborate more on this please? and what is the typical value for t_DEN_CSRVS as it is not provided in the datasheet.  

Hello Justin, 

Setting the DATA_VAL to 1XX would output a designated pattern instead of conversion data, correct.  A calibration can be done by using the available patterns to designate the delay between CONVST/CS goes low and when the MSB comes out on SDO as well as the delay for each next valid data on SDO. In some FPGAs an internal clock can be calibrated to this and can be used to read the data in from the SDO. In a sense replicating the RVS clock output internally. 

The delay between CONVST/CS going low and the 1st edge of RVS tDEN_CSRVS can be calculated by using DATA_VAL = 5 (data out is all 1s). --> The 1st edge of the SDO (MSB) would equal =  tDEN_CSRVS + tD_RVSDO.  tD_RVSDO is max 2.5ns, not making much difference and tDEN_CSRVS is less than 50ns then that is time saved and steps closer to 1MSPS.

Then using DATA_VAL = 6 (alternating 0s and 1s) the delay/rate of the data out can be calculated. 

Once that is calibrated, going back and setting DATA_VAL to 0xx will configure back the conversion data but now with the internal calibrated clock the data can be read at 66.67MHz.

Best regards, 

Yolanda

Hi Yolanda, 

Thank you for your response. I think I have an understanding now. However, I still have some questions.

1. Let assumed that my FPGA able to connect to the RVS of the ADC (with an additional ISOW), is there a range of typical t_DEN_CSRVS for ADS8681W? (As currently, I am still at timing analysis phase, I would like to check what is the typical scenario with its respective timing).

2. I would like to ask would the typical t_DEN_CSRVS to have a huge different between each invidual ADS8681W?

Hello Justin, 

It is not a huge variance between device to device, but there is also a temperature dependency on the delay as well. 

The current max value is set to ensure sufficient delay is given through temperatures up to 125C. If your system isn't excepted to be in a environment close to 125C there is a good chance that the delay could be about 10ns less 

Having access to RVS will also add insight into the conversion delay, since when CONVST/CS is high, the RVS reflects the internal ADC timing, a transition on RVS will signify the conversion has ended and CONVST/CS can be brought low.  This could also save possibly in the range of 10-20ns if not close to 125C. 

Best regards, 

Yolanda

Hi Yolanda, 

Thank you for the response. 

Currently, I am thinking to use multiSPI Source-Synchronous Internal Clock Mode to perform read and write performance. 

As my understanding on Figure 5-8. multiSPI Source-Synchronous Internal Clock Serial Interface Timing Diagram, the RVS did not show a transition which signify the conversion has ended (but it does for standard SPI, and/or source-synchronous external clock). 

Let me double confirm my understanding here, with multiSPI Source-Synchronous Internal Clock Mode, in order to achieve 20 bits of read data, all I need to do is
Step 1. At FPGA, switch CS from high to low after t_conv_max,
Step 2. At FPGA, wait for RVS to show a negative edge and capture the SDO MSB
Step 3. At FPGA, repeat Step 2 until I get my desired number of bits.
Step 4. At FPGA, switch CS from low to high then repeat from Step 1. 

With assumption that typical t_DEN_CSRVS will be less than 10ns (which is way far below 50ns as per stated in datasheet), it is possible to achieve 1MSPS data rate.

Please correct me, if any of the above statement is wrong.


The next part of the question would be on how could I do write (or configuration for the ADC) during multiSPI Source-Synchronous Internal Clock Mode? Or I am only allowed to use standard SPI method to do write?

Hello Justin, 

Your understanding is correct, with the exception of one thing, but that is probably because of my wording.  I meant that the  t_DEN_CSRVS could be about 10ns less than the max, so ~40ns. I am sorry for the confusion. 

With the Source Synchronous Internal mode and with the RVS available, then yes, the steps you mentioned would be ideal, and could get you close to 1MSPS, it could be slightly under or the full 1MSPS.

Best regards, 

Yolanda

Hi Yolanda, 

Thank you for the clarification.

I am curious on why the t_DEN_CSRVS is having a higher value than t_DEN_CSDO (which is below 10ns).

Aren't the RVS and SDO are related signals where RVS is the signal clarify on when the SDO is ready to be capture and since in standard SPI t_DEN_CSDO is less than 10ns, won't t_DEN_CSRVS should be around same value as t_DEN_CSDO?

Hello Justin, 

The timing constraint, t_DEN_CSDO, is the delay from the SDO going from tri-state to driven state. When CS is high, SDO is tri-state and when low it is driven. 

t_DEN_CSRVS on the other hand includes additional delays due to using a multi function pin (RVS) to output an internal clock (not just the typical, mostly static, internal status), on top of also the delay of enabling the data out and preparing to shift out data that would be synchronous to the clock out at RVS. That might require a couple of sacrificial clock periods to enable SDO and RVS to be synchronized. Additionally there is some possible drift over temperature which is where the max 50ns comes from.

Best regards, 

Yolanda

Hi Yolanda,

I did some calculation, and with an isolator in between, I did not manage to get my system to work at targeted 20 bits at 1MSPS. The total time taken for a cycle would be, t_total = t_CONV_MAX + t_DEN_CSRVS + 2*t_pd + 20*t_CYC_RVS = 1050ns (worst case, t_pd = 16ns, t_DEN_CSRVS = 50ns) or 1022 (typical case, t_pd = 7ns, t_DEN_CSRVS = 40ns).

As I only have one additional pin available at FPGA to choose between RVS or SDO_1, and connecting RVS does not seems to be helping me achieving the targeted rate. I would have to go for SDO_1. Do you have any suggestion on how dual SDO could help me to achieve 20 bits at 1MSPS?

Hello Justin, 

Using dual SDO would make it easier to achieve 20 bit since it cuts the number of clocks needed by 2. 

With standard SPI this would be achievable with SCLK = 32MHz, and with the 25MHz previously mentioned a ~920kSPS would still be achievable. 

Best regards, 

Yolanda

Hi Yolanda, 

When I read back ADS8681 datasheet, I noticed the following statement.
 "With regard to the digital isolator, the ISO7640FM is recommended for the following reasons:

• Supports > a 50-MHz SCLK and the required logic levels for operating the ADS868x at the full throughput
• Quad-channel device that facilitates excellent delay-matching between critical interface signals for reliable operation at high speed."

However, based on [FAQ] How to calculate the maximum SPI speed supported by a digital isolator? - Isolation forum - Isolation - TI E2E support forums, the maximum speed for SCLK for ISO7640FM seems to be much more below 50MHz (fSCLK<1/(4*pd(max)) = 23.8MHz) as per claimed in the datasheet. 

Hence, I would like to ask for understanding on the statement stated in the ADS8681 datasheet on how does combination of ADS8681+ISO7640FM able to achieve > 50MHz SCLK.