Part Number: ADC3663
Hello,
We are using ADC3663 for the settings : Sampling Clk = 20MHz, 2-wire, 16-bit, Bypass mode , wherein the DCLKIN = 80MHz is given to the ADC. When measuring the Output clk, DCLK = 80MHz but aren't receiving any FCLK, also no data is being captured. We aren't configuring via SPI and using the default settings as mentioned in the datasheet Pg-52.
1. Do we need to write any register setting via SPI?
2. Is there any relation between the DDC enable/disable and the decimation filter mode register settings?
Also, another observation being, when giving the sampling clk of 25MHz from Si5338 (Clock Synthesizer), we are able to capture the data and are receiving FCLK as well. Again, the ADC is being operated in the default settings without any SPI configuration.
3. What could be the possible reason for such abrupt behaviour?