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Original question:

ADC12QJ1600EVM: ADC12QJ1600EVM: ramp test mode, limited range

ADC12QJ1600EVM: ADC12QJ1600: test modes

Michael
Prodigy 120 points

Part Number: ADC12QJ1600EVM

Hello,

we have ADC12QJ1600EVM with Zynq FPGA using TI JESD204 IP HDL stack. The settings are JMODE3 (10bit resolution), Fs=500Msps, F=5, K=32. The FPGA design uses just one RX lane. It seems to be somehow working, QPLL is locked, rx_lane_data_valid is 1 so the FPGA accepts the data. 

I use the Ramp test mode for the first trials. The datasheet states that the ramp runs from 0x00 to 0xFF per octet. However, I see that it runs only from 0x00 to 0x9F. 

For Transport Layer Test mode, I see repeating pattern of 0x52248D2448. This is 5bytes which should repeat in my JMODE=3, but the pattern itself is totally different than what is in the datasheet
image.png

Any advice how to get result as in the datasheet?

Thanks Michael

 

  • +1
    Prodigy 120 points

    1. Regarding the capped ramp to 0x0 to 0x9F, is the reason that the ramp resets on the boundary of the multi-frame? F*K=160=0xA0

    2. Regarding the Short Transport Test Pattern, I found that EVM kit routes D2 lane to standard FMC D0 lane position, so I should look for D2 pattern 0x121-0x124. After rearranging 0x52248D2448, the 0x121... pattern is there. I need to use rx_lane_start_of_frame signal to store it with the start of frame boundary in mind.