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Original question:

DAC8168: Software Reset, Clear Code and LDAC_N

DAC8168: LDAC Pin Level Sensitive or Edge Triggered?

Bradley W Wiitala
Prodigy 120 points

Part Number: DAC8168

Hi,

I'm working with the DAC8168 and have success setting all the voltages. However, it seems that the LDAC pin is 'level sensitive' and not 'edge triggered' as implied by the datasheet. 

In other words, if I leave the LDAC pin low, the DAC output is immediately updated. 

I am setting C3-C0 at all zero's. 

Thanks,

Brad Wiitala

  • 0
    TI__Genius 17330 points

    Hi Brad,

    It's possible the device detects a low on the LDAC pin as an update. The timing diagram specifically shows that the LDAC has to be high during the commands, so your situation could very well be an example of how the device acts with a low LDAC. 

    What values do you write to the LDAC register? If any of these bits are 1, the output will automatically update with the 32nd clock cycle.

    Thanks,
    Erin

  • +1
    Prodigy 120 points

    Hi Erin,

    Thanks for the quick response. I'm not writing to the LDAC register. The statement below made me think that I could write to the input register when LDAC was low and the output would not change. I also posed the question to ChatGPT and it assumed the same think LOL. 

    "In asynchronous mode, the LDAC pin is used as a negative edge triggered timing signal for simultaneous DAC updates."

    I guess I missed the statement from the datasheet. 

    "If the content of a data buffer is not changed, the corresponding DAC output remains unchanged after the LDAC pin is triggered."

    Thanks for you help,

    Brad