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ADS1278 readings affected by Multimeter probing

Yashas
Prodigy 160 points
Other Parts Discussed in Thread: ADS1278, ADS1278EVM-PDK, THS4521

Hello,

I am using ADS1278 in conjuction with SM470 in my data acquisition system. I am consistently getting about 3 mV of mean data shift based on whether the AINP, AINN of a particular channel is probed or not. I used Channels 1,2 and 3 to verfiy this.

This same behaviour continued on ADS1278EVM-PDK though not on the same order but I still get about 0.9mV of mean data shift in the readings when the inputs are probed or not.

Any clues on why this is happening?

Regards,

Yashas

  • 0
    Prodigy 160 points

    Update:

    Data collected from ADS1278-PDK in the file attached.

    EVM1278-PDK 1,2,-1,-2V wDMM Analysis.docx
  • 0
    TI__Mastermind 43915 points

    Hi Yashas,

    My bet is that this with the input impedance from the ADS1278. You will notice that it is not that high in comparison to other delta sigmas as this is an unbuffered delta sigma converter. The input impedance, itself, is actually a function of the fmod speed set by the master clock to the ADC. The ADS1278EVM has a switch to enable or bypass THS4521 drive amplifiers, so it should be a quick test to see if the error is a result of the input impedance or not. Additionally, the input impedance is going to scale with modulator clock. Slowing down the modulator clock should increase the impedance seen at the modulator input.

    Regards,

    Tony Calabria

  • 0 in reply to Tony Calabria
    Prodigy 160 points

    Tony,

    Thanks for your reply. I did check putting the buffer in between and then bypassing it and the problem seems to come from the differential input impedance being low for the ADC inputs.

    In that case, is it possible to measure the performance/errors of the ADC alone? The errors will always be inclusive of the 'driver+ADC'.

    Regards,

    Yashas

  • 0 in reply to Yashas
    TI__Mastermind 43915 points

    Hi Yashas,

    What type of performance measuring do you have in mind? The value for the differential input impedance is calculated from the following equation -

    1 / (Csample X fmod)

    Where Csample is the equivalent capacitance from the sampling capacitor and fmod is the modulator rate. The modulator rate is derived from the master clock, so you can increase the impedance seen at the front end by slowing the master clock. The down side of doing something like this is that a lot of the internal timings and data rates will scale with it. The differential input impedance can scale with any kinds of error or variation in the master clock.

    That being said, you can do an input DC noise test by shorting the inputs together and looking at a histogram code variation to see how much noise is coming from the converter. Aside from that test, you are going to want to have a proper buffer to do any AC testing.

    Regards,

    Tony Calabria

  • 0 in reply to Tony Calabria
    Prodigy 160 points

    Hi Tony,

    I want to do a basic linearity test. My application requires high precision and in order to calibrate the system I am interested in getting the slope/line. I fix AINN at 2.5V and sweep AINP from 0.5 to 4.5V with 0.5V increments. I have already done a test for the input driver separately but it would be nice if I could do such a test only for the ADC without the buffer. So I can get a clearer idea which section needs tweaking and improvement. But according to the design explanation above, I cannot probe AINP and AINN directly to measure the input.

    I have recently learned that if the slew rate/GBP of the op amp is low, 2.2nF diff. input cap. may not be sufficient relating to the charge cap circuit internally. I traded off speed for low offset and low offset drift again for the reason that I need high dc precision. I am not using THS4521. I would like to discuss this as well and show you my schematic. Please provide your email address.

    Regards,

    Yashas