TLV5630

we have some problems with TI TLV5630 8 channels DAC during its programming.

In order to configure TLV5630 we follow the procedure:

                1. configure CTRL 0 register with value 0x004 to obtain internal 1V reference

                2. configure PRESET register with value 0x000 to set output at 0V after power-up

                3. PRE signal is set LOW (in order to reset device)

                4. PRE signal is set HIGH (in order to have device in normal operation)

                At this point, 8 output are at 0V (excluding offset on each channel)

 Now we try some procedures to configure outputs:

CASE 1:  LATCH signal (pin LDACn) is always at LOW value

                1. configure Channel A (register 0x0) with value 0x400 (desired output = 500mv, measured output = 500mV)

                2. configure Channel B (register 0x1) with value 0x800 (desired output = 1V, measured output = 1V)

                At this point, Channel A output decreases and measured output is 0V (PRESET value).

                This behavior is observed also when others output (Channel C to Channel H) are programmed after Channel A.               

CASE 2:  LATCh signal (pin LDACn) is moved HIGH and LOW

                1. LDAcn signal is set HIGH

                2. configure Channel A (register 0x0) with value 0x400 (desired output = 500mv)

                3. configure Channel B (register 0x1) with value 0x800 (desired output = 1V)

                4. LDAcn signal is set LOW

                At this point, Channel A is 0V (PRESET value) while Channel B  is 1V.

                This behavior is observed also when others output (Channel C to Channel H) are programmed after Channel A.

CASE 3:  LATCH signal (pin LDACn) is always at LOW value

                1. configure Channel B (register 0x0) with value 0x400 (desired output = 500mv, measured output = 500mV)

                2. configure Channel A (register 0x1) with value 0x800 (desired output = 1V, measured output = 1V)

                At this point, all 2 output have correct value.

                This behavior is observed also when Channel A is programmed after others output (Channel C to Channel H).               

CASE 4:  LATCh signal (pin LDACn) is moved HIGH and LOW

                1. LDACn signal is set HIGH

                2. configure Channel B (register 0x0) with value 0x400 (desired output = 500mv)

                3. configure Channel A (register 0x1) with value 0x800 (desired output = 1V)

                4. LDACn signal is set LOW

                At this point, all 2 output have correct value.

                This behavior is observed also when others output (Channel C to Channel H) are programmed after Channel A.

In case 3 and 4, we have seen a strange behavior too.

When all channels are configured, some outputs don't fix voltage at desired output but show 0V (PRESET value).

This behavior isn't static, this change with the programming register order.

For example, if we configure channels from H to A, output value is correct only for Channel A, B, D, F, H.

If we configure channels with this order (G, H, E, F, C, D, B, A) only the output C fault.

Probably we fault programming.

So, we have some questions:

1. exist a predefined order to configure output channels?

2. if this order exist, how we can configure single output avoiding other channels reset? Must we configure all output anytime?

In order to permit you a complete analysis, in attach you can find the schematic related to DAC.

All signals that you see are linked with FPGA and we can control them. DAC output are connected with amplifiers.

Do you see error? Do we change something in order to avoid behaviors described above?

Thanks

Regards

Mauro Vignali