I have to generate a sine wave using look up table. The DAC board uses differential inputs. Should the clock provided also be differential? Also should i provide differential clock pins of the fpga board? or should it be from the lpc connector? How can i provide dataclk? Does it have the same source as DACClk?
This is my code
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-- Company:
-- Engineer:
--
-- Create Date: 14:37:49 01/23/2013
-- Design Name:
-- Module Name: sinediffoutput - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use IEEE.STD_LOGIC_ARITH.ALL;
Library UNISIM;
use UNISIM.vcomponents.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity sinediffoutput is
port (clk :in std_logic;
diff_data : out std_logic_vector(7 downto 0);
diff_data_n : out std_logic_vector(7 downto 0)
);
end sinediffoutput;
architecture Behavioral of sinediffoutput is
signal i : integer range 0 to 30:=0;
signal data : std_logic_vector(7 downto 0);
signal data_temp : std_logic_vector(7 downto 0);
signal dataout : integer range -128 to 127;
type memory_type is array (0 to 29) of integer range -128 to 127;
--ROM for storing the sine values generated by MATLAB.
signal sine : memory_type :=(0,16,31,45,58,67,74,77,77,74,67,58,45,31,16,0,
-16,-31,-45,-58,-67,-74,-77,-77,-74,-67,-58,-45,-31,-16);
begin
sine_generation: process(clk)
begin
--to check the rising edge of the clock signal
if(rising_edge(clk)) then
dataout <= sine(i);
i <= i+ 1;
if(i >= 29) then
i <= 0;
end if;
end if;
end process;
data_buffering: process(clk)
begin
--to check the rising edge of the clock signal
if(rising_edge(clk)) then
data <= conv_std_logic_vector(dataout, 8);
end if;
end process;
buffer_to_diff7 : OBUFDS
port map(
I => data(7), -- Buffer input
O => diff_data(7),
OB => diff_data_n(7)
);
buffer_to_diff6 : OBUFDS
port map(
I => data(6), -- Buffer input
O => diff_data(6),
OB => diff_data_n(6)
);
buffer_to_diff5 : OBUFDS
port map(
I => data(5), -- Buffer input
O => diff_data(5),
OB => diff_data_n(5)
);
buffer_to_diff4 : OBUFDS
port map(
I => data(4), -- Buffer input
O => diff_data(4),
OB => diff_data_n(4)
);
buffer_to_diff3 : OBUFDS
port map(
I => data(3), -- Buffer input
O => diff_data(3),
OB => diff_data_n(3)
);
buffer_to_diff2 : OBUFDS
port map(
I => data(2), -- Buffer input
O => diff_data(2),
OB => diff_data_n(2)
);
buffer_to_diff1 : OBUFDS
port map(
I => data(1), -- Buffer input
O => diff_data(1),
OB => diff_data_n(1)
);
buffer_to_diff0 : OBUFDS
port map(
I => data(0), -- Buffer input
O => diff_data(0),
OB => diff_data_n(0)
);
end Behavioral;
