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Interfacing ADC to OMAP138 at >60MSPS

Y B.Z
Prodigy 215 points
Other Parts Discussed in Thread: LM138, ADC10080, OMAP-L138

Hi,

I am trying to design a board that will interface a high speed ADC to OMAP138

The ADC should be 10b@(>60MSPS), pereferably low power.

I would like to design it without glue logic if possible and verify the DSP can handle the 60MSPS and higher throughput.

Any idea on how to do it or design reference you can share ?

Thanks,

Yu

  • 0
    TI__Genius 12965 points

    Yu,

    Using the uPP (universal parallel port) of the LM138 it may be possible to connect the CMOS output ADC to the LM138.  We have not done this on any EVMs but it may be possible.  There is a document on the ti.com site that covers the details of the uPP on the OMAP.  You will need to check with the OMAP team to see if they can support you on uPP.

    http://www.ti.com/lit/ug/sprugj5b/sprugj5b.pdf

    I'm also attaching a summary document that goes over the uPP connection on the LM138.

    Ken.

    5732.uPP study.pdf

  • 0 in reply to Ken C
    Prodigy 215 points

    Thank you Ken,

     

    My primary concern is if I can connect an adc like ADC10080 (which has only CLK, DATA) and still guaratee a throughput of >65MSPS using the uPP.

     

    I have tried to post it on the OMAP™ Processors forum but still didn't get an answer.

     

    Regards

     

  • 0 in reply to Y B.Z
    TI__Expert 4340 points

    Yu,

    I support the ADC10080. I am not intimately familiar with the uPP interface, but I have made the following observations:

    - The uPP interface signals are: DATA, CLOCK, WAIT, ENABLE, START. The OMAP-L138 datasheet mentions that the use of ENABLE, WAIT, and START can be disabled and the CLOCK polarity is configurable. The ADC10080 simply outputs a parallel 10-bit word with a clock so it should interface OK from a logical perspective.

    - Looking at the OMAP-L138, the uPP supports up to 75Mb/s (75MHz CLOCK in SDR mode or 37.5MHz CLOCK in DDR mode). The speed should be OK as long as the ADC10080 is operated below 75MHz

    - The ADC10080 outputs are 3V logic. The OMAP-L138 has 3.3V logic inputs (when properly configured), so the bus should electrically interface OK as well.

    - Operating the OMAP-L138 uPP in the top of the speed range requires a good CLOCK duty cycle. Therefore, the ADC10080 must be provided with a clock that has something like 45-55% duty cycle.

    Regards, Josh

  • 0 in reply to Joshua Carnes
    TI__Expert 4340 points

    Yu,

    The ADC10080 does not output a separate clock with the data. The input sampling clock of the ADC must also be used to clock in the data on the L138. The ADC10080 d/s states that data comes out 1 to 6 ns (limit over temp) after the rising edge of the clock.

    The uPP interface on the L138 has a 4ns setup time and 0.8ns hold time requirement. The hold time is obviously met. At 75MHz, the setup time is met at worst conditions with 3.3ns margin.

    One should pay attention to the clock routing of the clock to the ADC and L138 to ensure similar edge arrival.

    Regards,

    Josh  

  • 0 in reply to Joshua Carnes
    Prodigy 215 points

    Thanks a lot Josh,

     

    Your answer confirms my thoughts (if both uPP and 10080 are working on Clk rising edge).

    The only thing left to verify now is if the uPP will support a throughput of at least 60MSPS without loss of data.

    For this, I am waiting for the L138 guys to answer...

     

    Thanks again,