DAC34H84EVM Rev D Schematics/Documentation - Urgent

KH,

Thanks for that. It appears that updated conector on REV D PCB is not compatible with HSMC (High Speed Mezzanine Card) specification. The pins that are allocated for 12v and 3.3v power on bank 2 and 3 are connected to ground.  Is there an adapter board that connects this board to HSMC?

can you please upload the schematics in orcad capture format. it looks likr they are made using orcad capture. it will save us all a lot of time to make the schematic in orcad while using the chip in our design. it will also save me the trouble of making the symbol in orcad.

thanks

Shailesh Khole

Khole,

Please see attached for the complete design package including the .dsn file and .brd file.

-KH

Thanks a lot.

you have saved me a lot of time re drawing the ADC schematic.

Shailesh Khole

Kang Sia, Are there any adapter boards that connects the REV D board to HSMC since the connector definition has changed?

Hello Chee-Boon,

I see that we have made a mistake on rev D to tie the 3.3V and 12V rails pins from the HSMC host boards to ground. The original intention is to improve the data signal integrity from our TSW1400EVM to our DAC EVM by adding ground in between the differential pairs. We were too focused on the TSW1400EVM and did not consider the back-ward compatiblilty with the Altera HSMC host boards.

One quick solution is to ship you a rev C board where the pins are not grounded. I will PM you offline to get your address.

We are also looking into changing the HSMC connector from a "D" header to "D-DP" header where every third single-ended pins are removed. This actually helped improve the signal integrity slightly. If you look at the Samtec page below, The QTH-060-01-L-D-DP-A (without the middle-ground pins) is rated for 9.5GHz of 3dB insertion loss when compared to the original QTH-090-L-D-A of 8GHz of 3dB insertion loss. I will confirm with the Samtec sales on this.

http://www.samtec.com/documents/webfiles/pdf/QTH.PDF

-KH

Hi KH,

Are you able to confirm whether there are plans to update fmc-dac-adapter to match the Rev D pinout changes for Xilinx FMC host boards?

Thanks

Cameron

Cameron,

The concern that Chee-Boon had is regarding the DAC EVM interfacing with existing Altera FPGA EVMs with HSMC connectors. There are single-ended nets (in between the differential pairs) on bank 2 and bank 3 that are connected to 3.3V and 12V on most of the Altera FPGA boards. On the DAC EVM, these nets are tied to ground for better signal integrity.

The FMC-DAC-adapter's HSMC connector at J2 do *not* have these net connected. Therefore, this will not be an issue when using the FMC-DAC-adapter. You can refer to the adapter schematic for more detail:

http://www.ti.com/lit/zip/slor102

-KH

Hi KH,

I’m trying to get the DAC board’s clock generator (CDCE62005) to achieve PLL lock (which is the first stage of getting the TI board commissioned).  I can see at power on that the D1 LED glows for a very short amount of time (possibly just a startup condition), and then I try to configure it through the GUI but I cannot seem to achieve lock (D1 glowing).  Note that this is in a stand alone mode – with the board not connected to the FPGA board.

The input source that I am using is the onboard 19.2MHz TCXO, and I have confirmed that the jumper (JP7) is loaded, giving this chip power.

The DAC evaluation users guide really doesn’t discuss how to setup the board, rather it just loads preconfigured files.  I can’t seem to get them to work either…

Would you be able to get explicit instructions on how to setup the GUI to achieve PLL lock (which would include selecting the secondary input, stating the input level voltages, AC-DC etc), or alternatively a configuration file which will achieve this?

Hi KH

My name is Andrew, Chee-Boon has been assisting us with the DAC board, and thus the previous question was from me.

I found another forum thread which had similar requirements, and you supplied a configuration file at one point.  I downloaded it and used it with my DAC board with some success.

http://e2e.ti.com/support/data_converters/high_speed_data_converters/f/68/p/224608/820143.aspx#820143 , Nov 19 2012 14:24 PM

Only after the DAC board has been powered down for a period of time, and then the configuration is loaded does the PLL Lock LED illuminate.  Thus if I load the config and then shut down the software, power cycle the board, open the software and load the config the PLL Lock LED will not illuminate...

I can see the PLL Lock LED turning on and off when I change particular settings (ie Input Source), thus I can see that there is still communication between the GUI and board.

In any case when the PLL Lock LED is illuminating I am not getting a clock on the DACCLK net.  I can see this via a CRO, as well as the DACCLK_gone alarm.  After PLL Lock has occurred is it only the CDCE Output settings which might affect the output, or are there other settings which might stop a valid signal getting to the output stage?

Thanks

Andrew

Hi Andrew,

I have attached an example setting file configuring the CDCE62005 with 983.04MHz VCO output and DAC34H84 in 2x interpolation mode. When you finished loading the file, go the CDCE62005 tab and double click on the wake up button. This should calibrate the VCO to achieve lock.

The default setting takes reference from the 2nd input of 19.2MHz crystal. You can always select the 1st input for external reference.

The CDCE62005 also has software that can help you configure the CDCE62005 settings given the reference and desired output frequency:

http://www.ti.com/litv/zip/scac105e

-KH

Hi KH

I dont believe that you added the attachment

Thanks

Andrew

sorry,

please see attached.

-KH

Thanks KH

Using your config, plus a few other fine tuning settings I have been able to get the DAC outputting.  I may follow up at a later stage to state what was different between this current config and the previous one

Thanks again

Andrew

Hi KH

Does the ISTR pins need to be connected if I am exclusively using sync?  The pin descriptions state that sync can be left unconnected but it doesn't say anything for istr..

I am not using parity, but I am not sure if I have control over the digital blocks "..to provide a sync source to the digital blocks.."  The main functional diagram suggests that the signal terminates at the FIFO..

Thanks

Andrew

Andrew,

The DAC34SH84has flexibility programming which control signal to use. The SYNCP/N pair, when compared to PARITY and ISTR, has the most functionality in terms of syncrhonizing the FIFO, clock divider, various digital logics, and also the on-chip PLL. The short answer is that this will depend on your DAC implementation.

Please take a look at the attached document, section 2. This should be able to help you quickly identify the synchronization signals for your implementation. The details can be found in the DAC34SH84 datasheet. 

-KH

Thanks, will look into it