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Good day,
We are using the ADC1672 from TI as it comes in its evaluation board. In our application we have a mother board that connects directly to the ADC1672 EVM board. We have tested the performance of the acquisition and it is good. However, if the input voltages are close to the saturation voltage the converted data gets distorted in a “twos complement wrapping around” form. This is described in the illustrations and text below. We have two hypotheses for the cause of this problem but would like to confirm about these with a TI FAE and see what the potential solution is for this problem.
Setup description:
The ADC1672 EVM is connected to a PCB that has a microcontroller. The micro interfaces with the ADC1672 and provides it with the signal to start conversion and gets the acquired data through I2C interface provided.
A differential signal is supplied to the ADC1672EVM. It centered almost at 2.5V. There is a small offset (about 0.05V) that due to the tolerances of the components we have we cannot control. However, we do not believe this would be the problem as within the ADC1672EVM module this signal is being fed to the THS4520 differential amplifier, which uses a precise common reference from the board.
From the ADC's data sheet:
Problem description
The examples below show data acquired from the ADC1672EVM interfacing with our microcontroller. The first two graphs correspond to input signals with a voltage leve well below the rails.
The graph shows the raw digitized data (already converted to decimal format) for an input signal with 1.1V peak as it is delivered by the ADS1672. It is clear that there is a wide gap around 8000000 (the Y axis on the graph is in Hex), which indicates that the signal is way below saturation.
The graph below shows the same data after the two's complement in a bipolar scale. We can now see that the signal has a small positive DC offset (the signal's mid point is above 0V)
Note that there is a small DC offset in the signal. It can be better seen in the signal before the two’s complement. The lobes at the bottom are larger than those at the top.
The signal below is close to the saturation point. However, because the differential driver is introducing a small DC offset, the level of the signal is enough to distort the output.
The "half point" in the graph below should have been at around 8388608 (i.e 2^23). If the signal was perfectly balanced, the red line would be a straight horizontal and the peak A should have been larger than B. The offset that produces the distortion.
The graph below shows the data after the 2's complement conversion. As expected the point B and all its similar points in the sequence have the sign inverted.
We believe that the problem is caused by an offset on the 2.5V reference voltage between the output of the REF5025 chip and the reference that the ADC1672 “sees”. At this time this offset is estimated to be at about 0.12V, which is enough to produce the errors seen above.
The question is how can we minimize the offset voltage on the board? Should we get a new board, replace components?
As plan B we could consider defining an amplitude band around the saturation voltages such that it covers the DC offset. Any sample that falls within the band is considered to be saturated and it must be either discarded or replaced with another value. This can be easily implemented in the FPGA that interfaces with our microcontroller.
Below is the resulting time series after the ADC data is complemented to two (bipolar scale). The red line was corrected and it distorted the signal, but the resulting distortion is significantly less than in the original case (blue)
This correction technique would not work if the signal was totally saturated as all samples would fall within the band to discard. There would not be any samples to replace them with.
