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ADC10D1500CIUT Clock coupling issue

Ramesh hhh
Prodigy 40 points
Other Parts Discussed in Thread: ADC10D1500

hi

We have used your part ADC10D1500CIUT in our application as a Analog to digital converter .This board Schematics design based on ADC10D1500CIUT reference Schematics. While testing it's observed, The clock frequency is given to ADC (1350Mhz)& with out analog input and plot the FFT using the 16K ADC samples the Clock frequency (Clock /2 =675Mhz)compoent is appearance in FFT plot . Kindly provide your suggesion for this issuevv

  • 0
    TI__Guru**** 189399 points

    Hi, Ramesh,

    Welcome to e2e, and thanks for your interest in our devices!

    This device is supported by our High Speed Data Converters (Audio is low speed data converter! ha ha).

    I am going to move your post to that forum.

    -d2

  • 0
    TI__Expert 3940 points

    Hi Ramesh,

    Please provide some details regarding the mode of operation: are you operating in DES / Non-DES Mode?  Are you operating in Demux / Non-Demux Mode?

    Kind regards,

    Marjorie

  • 0 in reply to Marjorie Plisch
    Prodigy 40 points

    Hi   Marjorie

    The modes are Non -DES Mode & Demux Mode

     

    regards,

    Ramesh N

  • 0 in reply to Ramesh hhh
    TI__Expert 3940 points

    2477.Maximizing GSPS ADC SFDR performance November 2012.pdf

    Hi Ramesh,

    The spur you observe is from the Data Clock (DCLK) which operates at 337.5MHz in Demux and DDR Mode.  There is some coupling in the package from the data clock output and it is sampled by the analog input to appear in the output spectrum.  See Slide 22 of the attached presentation for some more details.  (Actually, I just noticed that the clock speeds for the ADC10D1500 are incorrect on this slide, but you are using your own 1350MHz anyhow.)  One option to mitigate this spur is to operate in Non-Demux Mode, but that is a very fast data clock for the FPGA to capture...

    The attached presentation provides some more details regarding spurious sources in the ADC and methods of mitigation.  Let me know if you have further questions.

     

    Kind regards,

    Marjorie

  • 0 in reply to Marjorie Plisch
    Prodigy 40 points

    Hi  Marjorie

       Thank you for your valuabe information .In my Design  FPGA Cannot support 1.1 DeMux mode(ADC Frequency 675Mhz & DDS frequency Max 500Mhz ) & kindly give any anoter solution

    Kindly give the releated Document to add  dither.In My design RCOut1+/- pin connected to FPGA it may be created any issue

     

    Kind regards,

    Ramesh N

  • 0 in reply to Ramesh hhh
    TI__Expert 3940 points

    Hi Ramesh,

    Sorry, but there isn't another suggestion to mitigate that spur.  It is from the data clock coupling back into the analog inputs and takes place inside the package.  So, the option is just to change the clock frequency.

    We don't have any dither information specific to the GSPS ADCs, but I have seen many applications reports related to adding dither to ADCs in general, so perhaps you can search for the topic. 

    I don't understand the issue regarding RCOut1 - can you please clarify?  Are you using AutoSync?

     

    Marjorie

  • 0 in reply to Marjorie Plisch
    Prodigy 40 points

    Hi Marjorie

     I did not use Auto sync feature .The data Clock coupling issue occuring only in my case or all the series of this ADC (ADC10d1500 ) .If the same adc is configured  1:2 Demux mode how the harmonics is rejected(how the sfdr was achive  as per data sheet) & kindly provide the test results .

     When ADC was  tested Following configuration

    1)1:2 Demux Mode

     Clock frequency 1350Mhz_10dbm & analog Input 600Mhz-1250Mhz_2dbm

    In FFt Flot Data clok frequency amplitude(Fs/2 signal strength )reduced from -50 to -70 dbm but Fs/2-Fin component will apper & signal strength  is  -50dbm .

    2) 1:1 Demux Mode

    Clock frequency 800Mhz_10dbm & analog Input 600Mhz-750Mhz_2dbm

    In FFt Flot Data clok frequency amplitude(Fs/2 signal strength )is  -50dbm  but Fs/2-Fin component will not apper .