ADS5292 ADC resolution

Thanks Niels for pointing out the typos in the datasheet! The confusion is coming from datasheet conversation from ADS5294 to ADS5292. 12 bit, 14-bit information were mixed up. 

we target to release one version in March/Feb to address that and include more information. i attached a draft version first. the changes are listed at the end of datasheet. 

8446.SLAS788 RevC.pdf

ADS5292/94 is a 14bit ADC family. ADS5294's 14bit perofrmance is ensured by production test. while  ADS5292's 14bit perforamnce is based on design and char.  ADS5292's 12bit performance is ensured by production test. 

in short, ADS5292 can be used as 14/12/10bit device, both 2-wire and 1-wire mode. I extracted the new description as below: 

The ADS5292 is an octal-channel high-speed ADC with sample rate up to 80 MSPS that runs off a single 1.8-V
supply. The output resolution is configured as 14-bit,12-bit, and 10-bit if necessary. At 12-bit output resolution,
this ADC achieves 70-dBFS SNR at 80 MSPS. When the output resolution of the ADS5292 is 14 bit and 10 bit,
SNR of 72 dBFS and 61 dBFS (respectively) is achieved.

All eight channels of the ADS5292 simultaneously sample the analog inputs at the rising edge of the input clock.
The sampled signal is sequentially converted by a series of small resolution stages, with the outputs combined in a digital correction logic block. At every clock, edge the sample propagates through the pipeline resulting in a
data latency of 11 clock cycles.

The 14/12/10 data bits of each channel are serialized and sent out in either 1-wire (one pair of LVDS pins are
used) or 2-wire (two pairs of LVDS pins are used) mode, depending on the LVDS output rate. When the data is
output in the 2-wire mode, it reduces the serial data rate of the outputs, especially at higher sampling rates.
Hence, low-cost FPGAs are used to capture 80-MSPS/12-bit data. Alternately, at lower sample rates, the 12-bit
data is output as a single data stream over one pair of LVDS pins (1-wire mode), for example Fs<=65MSPS. The
device outputs a bit clock at 7x and frame clock at 1x times the sample frequency in the 14-bit mode.

Thanks!

Niels, 

1. the maximum data rate 960MBps requires very good FPGA timing control and clean power supply design to minimize jitter. thus typically it is not easy to do at a reasonable cost. Thus we suggest 2-wire mode for such a high Fs. this is the advantage of 2-wire mode for low cost FPGA.  if you are going to use 1-wire mode, it may be better for you to look at ADS5296A, which is in a much smaller form factor, 9 by 9 QFN, instead of 14 by 14 TQFP. because we eliminate unnecessary pins for 2-wire mode. 

2. if you read the last senstence of 3rd paragraph, you can see it refers to the 14bit mode.  

3. the comma typo is correct. we will address that in the offical release.

4. there are two concepts, output resolution and serilization factor. output resolution will affect SNR, while serilization factor does not. the reason to have 16 mode is due to FPGA example code. we know that some FPGA venders offer the deserilation code in 16 -bit format. if the ADC runs at low speed, it may not be a bad idea to use FPGA venders' code as is. however when Fs is higher, FPGA code has to be optimized for 14/12/10 bit resolutions.

Thanks!