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About DAC7742

Gk 110
Expert 2440 points

Other Parts Discussed in Thread: DAC7742

Hello,

I have a question about DAC7742.
There is a possibility that is occurring the latch-up at DAC7742.

Because,　The REFout is reduced to 30% of the original output.
As a result, The Vout reduced to 30% from original output voltage.
Vout & REFout is usually 10V output.

a, Power up sequence of error condition
 
   Vdd  ------->  Vcc  ----->  Vss
           (20ms)             (1ms)

b, Power up sequence of nomal condition

   Vdd  ------->  Vcc  ----->  Vss
             (1s)             (2-3ms)

(Question)
  1, Please tell me why the output voltage of Vout and REFout becomes abnormal.
  2, In the error condition,Output voltage of Vout and REFout has been reduced to about 30%.
     Is there a reason why the output voltage becomes 30%?

Best Regards,

  • 0
    TI__Mastermind 46290 points

    Manabu,

    Could you provide oscilloscope captures of the supplies ramping? That would be useful here.

    In this case the datasheet does provide a recommended power supply sequence of Vdd followed by Vcc/Vss which you have followed. Usually the digital power supply needs to come up first to load trim codes from internal memory for various parameters of the DAC depending on how comprehensive the trim scheme is. Most references have some level of trim and are the easiest place to notice if the read and trim process was corrupted. In this case it would seem that the analog supplies come up too soon for the trim process to complete.

    Looking at your supplies ramping will help us look into what is happening in your system more closely and give us something specific to attempt to replicate there.

  • 0 in reply to Kevin Duke
    Expert 2440 points

    Hi Kevin-san

    Thanks for your reply.
    Please confirm attached data.

    The customers have wanted to know if there is a rule of the power-up sequence.
    Can you be offer the recommend power-up sequence to me?

    Best regards.5556.DAC7742.pdf

  • 0 in reply to Gk 110
    TI__Mastermind 46290 points

    Ito-san,

    It seems to me the sequence is actually different for the pass and fail cases, not just the timing. In the good case the sequence is VDD, VSS, then VCC. The bad case shows Vdd/Vcc simultaneously followed by Vss - which is actually the worst case specified in the datasheet. Vss biases the device substrate so if Vcc comes up first you're likely to encounter issues. What is the green trace in the bad case?

    I am traveling right now and away from my lab, but I can see about getting someone to try to replicate this on our end. Like I said though - VSS should come up before Vcc. The good case shows pretty much ideal sequencing.

  • 0 in reply to Kevin Duke
    Expert 2440 points

    Kevin-san

    Thanks for your quick reply.
    The green trace of the bad case is REFout voltage.

    Customer was relieved by your comments(The good case shows pretty much ideal sequencing.).

    Does DAC7742 have a recommending time delay about power-up sequence?
    We want to know the specific numerical values​​ of powerup sequence,if there is a recommending time delay of Vdd & Vss & Vcc.

  • 0 in reply to Gk 110
    TI__Mastermind 46290 points

    Ito-san,

    We do not have characterization data concerning the timing of the power supply sequence. I am pretty confident that they could tighten their timing quite a bit without seeing any issues. In their scope captures the time division looks to be 200ms, the whole power-up sequence takes a full second. If they can maintain the order they show in the good case they should be able to shorten this time with no problem.