ADS5263 PLL problem

Hi,

We have received your inquiry regarding the ADS5263  PLL problem and hope to have a response to you very soon.

Regards,

Christian

Thanks,

To give you more details about my inquiry this is the exact settings of the ADS5263 that are measure on the board:

AVDD = 3.3V, LVDD = 1.8V, PD pin = 0V, RST pin = 3.3V (after hardware reset), SYNC pin = 0V, CS pin = 3.3V, INT/EXT pin tied to 1.8V with a 10Kohm resistor, ISET pin tied to 0V with 56.2Kohm, VCM tied to VOCM pin of THS4131 amplifier, CLKM = 0V, CLKP = 12.5MHz square signal (0 to 3.3V).

I'd tried different configurations for the ADS5263 even the default one (Normal operation, 16bit, 4 chanel, 1 wire 16 serial, 8x LCLK 1x ADCCLK), in each case the result was the same. No stability on the LCLK and ADCLK frequencies and completely out of range (always around 5Khz for the LCLK).

Regards

Frederic

Hi Frederic,

When measuring the ADS5263 EVM I am able to capture correctly with a 3.3Vpp-s.e. 12.5MHz, pseudo-square wave, on both CLKP and CLKM.  I would have to make some modifications to GND the CLKM input and drive single-endenly.  Is your clock input AC coupled as specified in table on pp 8 of the datasheet?  

Regards,

Christian

No.... and that's the point.

Do I need to put a capacitor between the generator and the pad CLKP?

And which value? 

So, I'd putted a capacitor between the square signal and the pad. I had tested with a 68 nF value and after I had doubled the value 136 nF. In each case, still no fonctionning...

I send you the schematic of what is exactly done at the present moment on the board

This capacitor value you have should be fine.  And I don't see any errors on your schematic.  Probing the LVDS outputs LCLK and ACLK on my EVM, I can dial the input clock down to 4MHz and up to 160MHz until the output frequency is not correct.  This is for 2-wire mode.  So the PLL is functioning correctly over this entire range of input clock.  

Your schematic does not show how are you terminating ACLK and DCLK into the FPGA.  What impedance does the receiver provide to these clocks?  Also, are you DC coupled into your FPGA receiver?  If so, what common mode voltage is the FPGA providing?

Regards,

Christian

So, here is monday morning news:

CLKP without any signal has a 700mV DC polarisation and the ouptput  LCLK run freely.

I had try to put a square signal with 1.5V of amplitude and 12.5MHz on the CLKP and had absolutely no effect.

So now, I'm starting to have doubt about the datasheet. Are you sure that the single ended mode is well describe?

Page 3 of ADS5263EVM board discuss about a single ended mode but with components that change it to a differential signal.

Is it absolutely sure that as it said in the forum that the input clock of the ADS5263 is the same as the ADS5295 which is compatible with the direct single ended mode (but with level of 1.8V max)?

Please I need a quick answer.

Thanks.

Could you be more precise about the way you send the CLK to the CLKP pin?

Did you tied CLKN directly to ground and put the generator with a capacitor on the CLKP pin.

To answer to your question, ADCLK and LCLK are directly connect to the FGPA (spartan6) on differential entries bank supply by 1.8V.

Hi,

After modifying my EVM  so that the CLKM pin is DC grounded I see the same result as you see.  When I AC ground the CLKM pin with 2.7nF  I see proper operation.  It looks the CLKM pin must be AC grounded and not DC grounded for single-ended clock configuration.  I will confirm with the design team and we will update the datasheet accordingly if this is the case.

Do you have possibility to AC ground the CLKM pin on your EVM and try this?

Thanks

Christian 

By chance it was possible to cut the wire on the CLKM pin on the board.

I'd putted a capacitor and now I have the good result.

For your information I use the ADS5263 with the built in low pass even tap filter with a decimation rate of 4 in 16bit, wordwise, two wire mode.

In that configuration ADCLK is Fs/8 and LCLK is Fs. The datasheet don't describe at all that kind of case when users want to enable filters with decimation rate.

Just "a last word".

There's four ADS5263 on my board, running with a common signal CLKP at 12.5MHz.

Each chip receive the same configuration, PD and SYNC signal. The goal of this application is to sample 16 channels at the same time.

So, finaly, in conclusion, to sum up, with the modification on CLKP and CLKM.......... it works!

Regards.

Frederic

Hi Frederic,

Thanks for giving us the "last word". It is refreshing to hear our users' success stories since this forum is typically used to communicate only problems.

Regarding the ADS5263 datasheet, we will update with more details for single-ended clock drive and also look to provide more details on other device configurations, as you mentioned previously.

Thanks,

Christian

Sorry.... I was too much optimistic....

The new problem I see in my application is that the ADCLK and the LCLK could have opposite phase compare to others from another chip.

Even if I activate the SYNC signal (register address $2, bit 13), and put a High pulse of duration 100ns on the SYNC pin, the ADCLK have not the same phase (wihich is very important if i want to precisely sample and process 16 chanels at the same time).

Supply, comand signals and CLKP are common for the 4 chips.

Could you check with the design team if there is a way to be sure that the PLL start the same way or can be reset to achieve a proper common sampling.

Thanks

Hi Again,

Can you confirm the following in your setup:

1)  1-wire or 2-wire LVDS interface to FPGA?

2) The same rising edge of the CLKP signal to all 4 DUTs is occurring simultaneously at each DUT.

3) The rising edge of SYNC pulse to all 4 DUTs is occurring simultaneously at each DUT.

4)  After power up you are doing either a hardware RESET or software RESET to all DUTs.

5) Is the phase of the ADCLK and LCLK random or systematic after several initializations of the DUTs?

Thanks

Christian

1) Two wire LVDS 16bits wordwise mode. I'd checked also the connectivity by putting all chips in ramp test pattern mode to see if I was able to receive correct samples.

2) The same edge on CLKP pin is apply to all converter (checked on the pin of each converter)

3) The same SYNC signal is apply to all converter (checked also on the pin)

4)    a)At power up PD pin = 1, SYNC pin = 0, CLKP pin = 0, CS pin = 1 on all chips

        b) after a delay of 1ms there is a hardware reset on the RESET pin  (pulse LOW  of 200ns duration)

        c) after a delay of 200ns the configuration of the four converter start. The configuration is send at the same time to all converter and it's start by an another RESET (software in this case) by putting bit 0 at 1 in the register $0. During all the configuration time, CLKP is hold to 0 and PD to 1.

The configuration send is as follow:

$000001  : reset software
$310111   : CH4, LP filter dec4, dec4, filter on
$300111   : CH3, LP filter dec4, dec4, filter on
$2F0111   : CH2, LP filter dec4, dec4, filter on
$2E0111  : CH1, LP filter dec4, dec4, filter on
$380002  : Output rate dec4
$290002  : Enable digital filter, average off
$28800F  : Enable word wise mode, all chanels
$022000  : Enable SYNC pin           
$46880D : Enable serial, 16bits, pad off, Msb first, 2's comp, two wire mode
$250040 : Enable ramp test pattern

        d) after configuration PD is put to 0 and CLKP start to be active after 70µs to respect the wake up time

5) The phase ramdom each time. When the first SYNC signal is apply, I see that edge of ADCLK start to be synchronise but with complete opposite phase.

So, I understand the SYNC signal as a RESET that effect only the decimation stage and not the PLL.

On the attached file you can see one case of the problem.

clk adc is the signal send to the CLKP pin.

sync adc is the signal send to the SYNC pin.

adc frame is the image for the four ADCLK signal after the input diff buffer in the FPGA

adc clk is the image of the four LCLK signal after the diff buffer (the frequency off LCLK is divide by two in the FPGA just for the observation)

So, I hope it's clear with enough details for you.

Frederic

Please, I need a quick answer.

We have already produce five boards and five another are waiting.

Thanks

HI,

I don't have the answer at the moment but can suggest a few things to try while I investigate further.

Can you change your initialization sequence such that PD=0 and a CLKP signal is present before step 4b (hardware reset) in your previous post.  Try this first.  If this shows no change, then in addition do the following:

Set the PHASE_DDR value from REG 0x42 D<6:5>. Note that in order to write to these bits the register must be enabled by also setting D15=1. See Figures 75 and 76 in section ‘PROGRAMMABLE LCLK PHASE’ of the datasheet. These bits set the relative phase between LCLK (bit clock) and ADCLK (frame clock).

The four possible values of REG 0x42 to try all four phases are as follows:

$428000

$428020 

$428040 

$428060 

Thanks,

Christian

Hi,

I'd tried your suggestions.

With PD = 0 and CLKP send before hardware (or software) reset, each converter start in a different phase state (as before).

I can see that after register initialisation, the LCLK and ADCLK reach the good frequencies value but  again with a different phase and after the SYNC signal, I have the same behavior. One or two frame (depending of the initial start of the pll) signals are in opposite phase.

I'd tried also different values in the Phase DDR register. I can see that LCLK match the specification of the datasheet, concerning time before or after rising edge of ADCLK but has no effect on the phase of ADCLK with the SYNC signal. The four converters are still not sampling at the same time.

Frederic

Hi,

Another point.

I have removed the output decimation rate and the numerical Low Pass filter in my configuration and keep the 2 wire mode and the SYNC signal enable.

CLKP is still 12.5MHz.. So, now at the output I have 50Mhz on each LCLK and 6.25MHz on each ADCLK.

But... the result is the same. The ADCLK don't have the same phase even after SYNC signal.

So now, i'm afraid to ask my last question. What's wrong?

Frederic

Hi Frederic,

I do not see any obvious errors in your initialization and power sequencing.  I am trying to replicate your configuration with a 2nd EVM in our labs to see if I can observe the same problem.   I'll will update you when I have some results.

Thanks

Christian

Hi Frederic,

We should have measurements with two ADS5263 EVMs today.  However, my thought was that this 'observation' should be evident on a single device by measuring the setup time from rising edge of SYNC pulse to the rising edge of the 'settled' frame clock (as opposed to the 'unsettled frame clock.)  By unsettled, I mean that in time period just after the SYNC pulse the duty cycle and period of the frame clock is not as expected as the synchronization is occurring.  Eventually, the frame clock is as expected in frequency and duty cycle.  The time for this to happen must be deterministic in order to synchronize across DUTs.  

So I captured the ADCLK of 1 device ten times triggering off of the SYNC.  In all ten cases, the settled frame clock occurred at the exact same offset from the SYNC pulse and at the same phase (rising edge of ADCLK).  I am unable to observe the ADCLK occur at a half cycle offset from this value which would indicate a phase inversion.

What is the pulse width of your SYNC signal?  I am using a single trigger pulse with a width of 5us. With what frequency do you see the phase inversion (i.e. probability of phase inversion-how many SYNC pulses must you capture before seeing an inversion).  Should I have seen this happen once in ten tries?  Is each ADC as equally probable to show a phase inversion?  Can can you measure the time delay from SYNC pulse to synchronized and settled ADCLKs for several captures?

Thanks

Christian

Hi,

My thought is... my explanation are confuse. Sorry, it's the French syndrome.

I'd tried different width of sync signal, 50ns to 500ns, on different phase of CLKP (rising edge, falling egde) What I understand is SYNC is rising edge sensitive, no matter of duration.

The phase inversion appear after the first SYNC signal (I'd send you before a pdf file which shows you the case).

The phase inversion depend of the way of the converter start because what I see clearly is that the response time is different on each converter. By response time I mean the time for the converter to reach the good frequency value on LCLK (4*fs with 2 wire mode or fs with 2 wire and decimation by 4) after applying the CLKP signal.

So, sometimes, when I'm lucky, the four converters start the same way and the phase is good. But in most of the case, one or two (not necessarily the same) have opposite phase.

SYNC signal has a period of 200ms. After the first SYNC, the system has no more evolution. ADCLK keep their respective phase. In my application, SYNC signal and CLKP have the same reference time, and are synchrone.

Frederic

Bonjour Frederic,

Pas de probleme.  Je comprends votre anglais parfaitement.

Since you mention SYNC and CLKP are synchronous, do you have the ability to introduce a phase offset in only one of these signals with respect to the other.  If so could you try this with several shifts (90deg, 180deg, 270deg)  I will try the same.  

Regards,

Christian

Hi,

Did you find anything new?

I'm still stuck. The test on the SYNC signal did not give any improvement.

Frederic

Hi,

Some news?

Frederic

Hi Frederic,

Yes, I have some news.  I am now measuring two EVMs by providing the same input clock and SYNC pulse to both.  The SYNC pulse is asynchronous with input clock, therefore, every time I manually send the SYNC pulse the relationship between its rising edge and the input clocks rising edge is random.  When doing this experiment over and over many times with the SPI configuration you provided, I cannot see an inverted frame clock. The two frame clocks are synchronized within a deterministic time always.  This experiment uses a 20MHz sine wave input clock driving deferentially.  

However, when changing the input clock frequency to 12.5MHz I do see exactly what you describe; one frame clock 180deg offset from the other.  So now I must confer with the design team to understand why.  I will update you soon.

Regards,

Christian

Ok,

I can't say I'm please, but in a way it is "a not so bad news". I'm not alone now...

Did you try also with a differential square clock 12.5MHz signal on the input?

Bad working is related to the single ended mode?

Thanks.

Hi Frederic,

I think I was mistaken when I reported an inversion in the frame clock  as I am unable to repeat this result over as many as 50 tries, including resetting devices and clocks. I think my scope probe was inadvertently touching the ADCLKM trace on one of the EVMs instead of the ADCLKP trace and, hence, the inversion.

This made me think of how you are determining the inversion.  I recall a screenshot you provided that looked like a chip scope from within the FPGA.  Can you comment?  Is it possible for you to probe the ADCLKP pins at the ADS5263 DUTs directly to eliminate the FPGA from the equation?  Also, we can continue this conversation offline if you prefer.  Please provide me your email address and I will contact you directly.

Thanks

Christian

Hi,

you'll find in the attached file the measure on the scope.

C1 is the ADCLKP pin  of ADC 1

C2 is the ADCLKP pin of ADC 2

C3 is the common SYNC signal

C4 is the common CLKP signal

My email: frederic.barraque@ixblue.com