Dear Mr Harsha-san
Hello,
Please allow me to have questions in place of Seishin ( My colleague) because he cought a cold today.
Thank you for your answer to seishin !
I would like to have additional questions in addition to Seishin's thread
http://e2e.ti.com/support/data_converters/precision_data_converters/f/73/p/395116/1399634#1399634
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# Question1
Is the timing diagram in attached sheet ( my understanding) correct? ( Thank you for your answer to seishin)
# Question2
My understanding is CDAC acquire the analog voltage of AIN1 when SW1=SW2=AIN1.
In this time, customer's concern is voltage rise depend on input cap..
ADS7825 acquire the voltage just at the edge of BUSY goes UP? ( My hope is , there are
No concern about the A/D conversion result even though we can see the rise of analog voltage ..... Is it correct?)
#Question3
From Customer's test result, AIN1 analog voltage start to fall to 62mV ( seishin's thread) when they had selct AIN2.
In this time, SW1/SW2 swtitches from AIN1 to AIN2. Here is the question.
Don't you have any additional switch (SW_x) who discharges the parastinc cap to ground in front of the SW1 ,, do you ??
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Our cusomer had using TI/BB products long time ( and will be), but they ahd jut found out the phenomenon in their circuit.
They want to fix the problem but they want to know the internal mechanism to estimate their workaround is correct or not by themselves.
Our customer is so in hurry , so , please adivse me if available, tommorow, hope to within 2days....
Please allow us such a complicated issue..
Best Regards