clock required for ADS1299

Hi Brian,

In my case I am not able to set the SCLK for SPI to MAX 20 MZ . Even though I am generating 20 MZh I am getting the SPI clock only till 12 MHZ.
Okay we are trying to do some initial reg reading of ADS1299 that is address 0x00 (CONFIG 1) . We are supposed to read this reg to validate the chip , but I am not able to do so .

When reading the register I am sending the opcode RREG for address 0x00 and number of bytes to read -1 .The exact sequence of my MOSI form master is as follows :-

1. RREG

byte 1 - 0x02 - clock cycle 1(8 clk cycles)
byte 2 - 0x00 - clock cycle 2(8 clk cycles)

So in the third 8 clock cycle I am getting 0x00 in MOSI .

Now Sequence for MISO from the slave is as follows :-

The MOSI line is pulled to low at all three 8 clock cycles , that is I am getting a 0x00 for all the three 8 clock cycles , which is totally wrong.Why is it so ?

In short let me say it again ,the slave is not giving any data when I am trying to read from CONFIG1 register. Can you tell me If I require to give any SDATAC or reset or WAKEUP command before reading the registers ? or is it because of clock which I am using ? . The clock right now I am using is 2 MHZ (SCLK) . with a delay of 2 us between the subsequent clock cycles. Ho do I proceed ?

Thanks
Rahul

Hi Brian,

I forgot to add one more info . I am configuring my ADS to operate in MODE - 1 , that is CPOL(polarity) = 0 and CPHA(pahse) = 1. Is this correct ?

Rahul,

Those are the correct SPI polarity and phase settings.

Brian

Hi Brian,

Should provide any delay between SDATAC and sending of opcode RREG. If so how much ?

Thanks
Rahul

Hey brian,

Thanks for your valuable inputs. I just want to clarify one more point. In ID control register Address = 0x00 , since it is read only register . I am trying to read this register now , I suppose I should be able to read 0x1E from it because the definition says :-

Bits[7:5]       Not used

Bit 4           Must be set to '1'

Bits[3:0]     Factory-programmed device identification bits  1110 = ADS1299

But its is also told in data sheet that after reset that is power on, the register will be reset to 0x00 . So I am able read only 0x00 from it through RREG. Is this the  way it should be ? 

Thanks

Rahul

Hi Brian ,

Its page number 39 of ADS1299 datasheet they have mentioned the Reset VALUE(HEX) for Address 0x00(ID reg) as 0x00.

thanks
rahul

Hey Rahul,

That is an error in the datasheet. The detailed register description contains the correct values.

Brian

Hi Brain,

Yes I am getting 0x3e from ID register . thanks a lot.

Regards
Rahul

Hey Brian,

Have a situation where I expect 11 clock cycles from MASTER(AM437x) to SALVEADS1299 but when I actually probe the lines I get only 1 clock cycles. Let me explain what exactly is going on . My flow looks like this .


SDATAC - opcode 1 - 0x11

delay of 2us

WREG command for 8 channels : - opcode1 - 0x40 | 0x05 (writing 8 channel registers for setting it into test mode)
opcode2- 8-1

Now when I probe on to clk and MOSI . I am able to detect clock only for SDTATC and after that I do not get any clock for WREG . This means it is not sending write command to slave . But why is this happening?

Now when I try to send multiple WREG command to my slave like some 5 times I start getting WREG signals on my probe lines(clk,MOSI) . Why does it require multiple WREG commands to send a write command to my SLAVE ?

I am attaching the probing signals 

Thanks
rahul

Hi Brian,

After setting the registers of  ADS1299 for Test signal generation  and then issuing RDATAC or RDATA , I am getting inconsistent values from all the channels . The values from all the channles are not same . I have learned that the values from all the channels should be approximately same resulting in overlapped  Square pules . Is this correct ? These are the register configuration I am using : -

CONFIG1           =  0xD6

CONFIG2           =  0xd0

CONFIG3           = 0x74

LOFF                  = 0x00

CH1                    = 0x65

CH2                    =  0x65

CH3                    = 0x65

CH4                    = 0x65

CH5                    = 0x65

CH6                    =0x65

CH7                    =0x65

CH8                    =0x65

BIAS_SENSP    = 0x06

BIAS_SENSN    = 0x02

LOFF_SENSP   = 0x00

LOFF_SENSN  = 0x000

LOFF_FLIP       =   0x00

LOFF_STATP   = 0x00

LOFF_STATN  =  0x00

GPIO               =  0x00

MISC1              = 0x00

MISC2            = 0x00

CONFIG4        =0x00

and My values are :-

But the expected values is some 1.4 mv (input short). But the values  that we read is so huge. Why is this happening, can you provide some  suggestions on this? . 

Thanks

rahul

Hi Brian ,

I have started getting values from ads1299 chip in RDATAC mode . I have set config 1 register for 250 sps. I am trying to read values for internally generated test signals.

So I am able to get my positive phase of around 1.8 mv and -1.8mv . But the problem is, I am missing my drdy a lot . The time between two consecutive drdy is around 2ms and even less according to catapulted in my case but according to data sheet it is 4 ms . Why is this happening ?

I do not want to miss my samples (drdy ) . Right now my frequency of(master that is processor and not the ads) operation is 2 MHZ . Should I increase it ? What can I do to increase the time difference between two drdys ?

Thanks
rahul

Hey brian,

How are you brian, hope you are going well.

I am facing one more problem while reading the data . Here is my problem . After configuring all the 23 registers and when I try to read the data. sometimes I get  zeros on my MISO lines from all channels while trying test signal generation. I have verified that clock is present for this duration.

RESET

SDATAC

msleep - 16

WREG configure all 23 register for test signals

RREG read to verify all the registers are written

START

msleep 16

RDATAC

Start capturing the data .

So sometimes in 10 trial to read the data I get data only  6 times. Can you please suggest something on this  . I feel this very incontinent.

Regards

rahul