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Frequent questions

  • [FAQ] AM625: Booting AM62x with Minimal DDR

    Part Number: AM625 This FAQ answers questions about minimum DDR requirement on AM62x, boot-time memory usage, and what changes are needed to boot successfully with reduced DDR.

  • [FAQ] TDA4VL-Q1: ADC AIN7 measures a higher voltage than expected

    Part Number: TDA4VL-Q1 Other Parts Discussed in Thread: TDA4VL , TDA4VH When using the MCU_ADC0 or MCU_ADC1 on TDA4VL or TDA4VH, the voltage measured on ADC0_AIN7 or ADC1_AIN7 has a higher voltage than expected (i.e., for an expected voltage of 0.8V…

  • [FAQ] TDA4VH-Q1: Testing functionality of ring accelerator

    Part Number: TDA4VH-Q1 Hi, Could you please guide us on method to inject error on ring accelerators.Thank you.

  • [FAQ] TDA4VEN-Q1: C7x reset from CCS issues double page Fault

    Part Number: TDA4VEN-Q1 Trying to reset c7x through CCS issues a double page fault.

  • [FAQ] AM625: OSPI Access Across Different Cores

    Part Number: AM625 Other Parts Discussed in Thread: AM62P , AM62L On different TI SITARA MPU SoCs, lets have a look at SoC wise cores which have access to the OSPI module/Controller in the current MCU+ SDK Software offering. Please refer the table below…

  • [FAQ] AM625: How to configure Timer in Interrupt mode

    Part Number: AM625 Other Parts Discussed in Thread: SYSCONFIG Lets have a look at the implementation of application using a TIMER module(DM TIMER) in Interupt mode of operation. The application code can be used as it is or as a baseline for configuring…

  • [FAQ] AM62D-Q1 Custom board hardware design – AUDIO-AM62D-EVM Audio Functionality Implementation Related Queries and Design Notes

    Part Number: AM62D-Q1 Other Parts Discussed in Thread: AUDIO-AM62D-EVM Hi TI experts, I am planning to reuse the AM62D-Q1 AUDIO-AM62D-EVM schematics for my custom board design. I see the below schematic sections (pages) added to the AUDIO-AM62D-EVM…

  • [FAQ] AM6421: RESETSTATz output during ROM boot

    Part Number: AM6421 Hello, During a successful QSPI boot, I have captured the following signals: MCU_PORz, RESETSTATz, OSPI_CLK, OSPI_CS. I'm observing that roughly 35mS after RESETSTATz goe high it has a 160uS period where it drops low. Looking at…

  • [FAQ] TDA4VH-Q1: How to configure the SerDes lane for PCIe, USB, Ethernet, and Display in Linux?

    Part Number: TDA4VH-Q1 The high speed interfaces on the TDA4x share the SerDes lanes. The lanes can be muxed for different interfaces, but how can I configure them within Linux?

  • [FAQ] AM2754-Q1: Working Configurations for 8S-8S-8S on S28HS512T Serial NOR OSPI Flash

    Part Number: AM2754-Q1 Other Parts Discussed in Thread: SYSCONFIG In MCU+ SDK 11.02, the OSPI and Flash examples are configured by default to operate at the highest protocol: 8D-8D-8D. For configuring 8S-8S-8S SDR Protocol on S28HS512T Serial NOR OSPI…

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