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AMC7820 Rise time

anita oommen
Prodigy 60 points
Other Parts Discussed in Thread: AMC7820

The datasheet for AMC7820 shows on Page 6 that the rise time and fall time of the clock signal for the IC has a maximum rating of 30ns.

1. In a continuous mode of operation of the chip what will happen if the rise time increases beyond 30ns.

2. Is there a possibility that the chip will be damaged?

3. Will keeping a buffer for the SPI lines help. If so what should be the criteria to select such a buffer.?

4. Is it possible to provide SPI lines to multiple AMCs if the rise time of the SPI is kept within 30 ns?

  • 0
    TI__Genius 11750 points

    Howdy anita,

    1. The 30ns Max Rise/Fall time spec applies to any acceptable SCLK freq, as well as any other digital signals.

    2.  If the Rise/Fall time is greater than the value listed you will more than likely get degraded timing performance, and the digital lines may be more susceptible to any external noise.

    3. Adding a buffer will definitely help meet the specified rise time, the parameter to search for is an OP AMP with a  fast slew rate.

    4. Yes, the SPI lines can be applied to multiple AMC units, but each part should have a unique CS signal so they can be accessed individually.


    Best Regards,

    Matt

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