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ADC121S021 Serial Timing question

skikingmg
Prodigy 90 points
Other Parts Discussed in Thread: MSP430FR5739, ADC121S021

I'm using an ADC121S021 hooked up to an MSP430FR5739.  I am getting incorrect data back from the converter.  I am wondering if it has something to do with the serial timing used or sleep/normal modes of the converter.  I've attached logic analyzer captures of the serial communication.  the clock is set at 1MHz, CS line is active (low) for 239ns before serial clock begins.  For now the ADC1215021 is connected directly to the VCC used for the MSP430 processor (3.08V), a resistor divider is placed providing 2.37V at the VA pin of the device.  Thinking this may be an issue with the device not starting up in normal mode, I attempted another test, where one message was sent bringing the CS line high after the first 10 clocks (should bring device out of sleep mode per datasheet), then readings were done leaving CS low.  This doesnt seem to produce correct results.  Any ideas on what changes I could make to get valid data out of the converter?

  • 0
    TI__Guru 54766 points

    Hello Skikingmg,

    Be sure to properly bypass the Va pin. Several "Sticking" MSB's can usually be traced back to poor bypassing or a poor supply.

    Your divider may be too "soft" (high impedance).

    Be sure you have at least a 0.1uF ceramic cap right across the Va and GND pin, and a 10uF (or more) near by. I would use 100uF since you are using a resistive divider.

    You also need at least 1us between CS going low and the first clock to allow for power-up (tSU). Add a 1us delay before the first clock pulse.

    Regards,

  • 0 in reply to Paul Grohe
    Prodigy 90 points

    Thanks Paul,

    I realized that at some point I may have crossed the VA and VIN lines, so I've "re-breadboarded" this with a new ADC121S021 device to remove the chance that the other chip had been damaged.

    I added a 100uF cap and a 2.5uS delay.  The divider used is 2x 9.5kOhm resistors. Also I am now using what should be a more stable supply instead of the MSP-FET430UIF source I've placed in a 3.3v LDO supplying just the processor and the ADC. 

    I'm still not able to get the expected response of 2048.  Should I be forcing the chip into "Normal Mode" every time I power up? The below logic capture was the second of two readings performed after power up.

    Thanks

    Mark

  • 0 in reply to skikingmg
    TI__Mastermind 24850 points

    Mark

    Paul asked me to comment on this.  Unfortunately your problem is not obvious to me either.  By the sounds of your problem description, I believe you fully understand the oprationoperation of our ADC.  As you have noted, it is important to discard the first conversion result after power up since it can be unstable.  I am curious, do you keep getting the same output code on the 3rd, 4th and 5th conversion result after power up?  I am trying to determine if you are experiencing some sort of settling issue.  I suggest if possible that you probe the supply pin and input pin with an oscilloscope.  I want to see how stable the input us.  Paul made a good suggestion to bypass the power pin since that is the reference voltage for the ADC.  I would also suggest putting a 0.1uF capacitor across the 9.5k resistor to ground (VIN to ground).  I just want to make sure that the input to the ADC is totally stable.

    Your comment about forcing normal mode after power up is not needed.  that automatically occurs once you bring CSB low after power up.  you just need to discard the first conversion result following that occurrence.  your description makes me believe that you understood this already but I am mentioning this to make sure.


    If probing the supply pin and VIN pin doesn't show any problem, another suggestion would be to keep CSB low after the first assertion.  the ADC will now permanently stay in normal mode and we would eliminate any concern about coming out of shutdown mode.

    I will continue to monitor your progress to see if any of my suggestions help.  I will also send you a friend request so you can contact me directly for future support on this.

    Chuck

  • 0 in reply to Paul Grohe
    Prodigy 90 points

    Paul/Chuck,

    Thanks for looking into this with me.  It turns out that the issue is (as you suggested above), related to the high impedance input and (as  you suggested below) also related to a lack of stability on the input.  I've added a cap on the input and am getting much more stable and predictable responses now.  Note that in the actual product design I'll be monitoring a buffered transducer output (not a resistor divider), but I have implemented an RC after the signal buffer to help ensure I don't encounter any issues of this type.  I attached two captures to illustrate the analog input signal before and after the modification.

    Before cap was added to VIN (channel 3 input signal in blue varies from 1.231V to 1.47V)

    After cap was added to VIN (channel 3 input signal in blue varies from 1.331V to 1.341V)

    Thanks for all the help!

    Mark

  • 0 in reply to skikingmg
    TI__Mastermind 24850 points
    as you can imagine, we all learn from trial and error
    I'm glad that you were able to resolve this quickly
    Chuck