Questions about ADC128S052Q

Hello Tsuyoshi,

#1. I believe VA, since it needs to be able to swing above and below VA/2 to balance the charge on the sampling cap above and below VA/2.

#2. No. The ADC128S series is a SAR (Successive Approximation) converter, which compares VA/2 and VC as "Higher" or "Lower" for each clock cycle until it reaches the LSB.

The reference voltage is NOT regulated or sampled internally. Any changes in VA will affect the VA/2 reference into the comparator, and thus the current reading during the last 13 clock periods. This is why it is critical that the VA be clean, stable and well bypassed to achieve optimum performance.

#3 There are ESD diodes from the inputs to VA. See Figure 37 on page 16. If VA is below the input voltage, the upper ESD diode will forward-bias and clamp to the VA. The ESD diode is taking the current and must be limited to less than the Abs Max input current (10mA). I would limit to less than 1mA - or about 1K series resistance for every volt over VA.

Note that if there is enough current available at the input, this may cause the VA line to be pulled up to a random voltage (until something on the line starts to conduct). If this is condition is expected to occur regularly, a clamping Zener should be used on the VA line to ground (to prevent the VA line from being pulled too high), and a Schottky diode between the input and the VA line to take the stress off the internal ESD diode.

Regards,