• State Resolved
  • Locked Locked
  • Replies 10 replies
  • Answers 1 answer
  • Subscribers 49 subscribers
  • Views 694 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Use external clock with ADC12J4000

Michael Robertson52
Prodigy 180 points
Other Parts Discussed in Thread: ADC12J4000, LMK04828

Hi All,

Bought a couple ADC12J4000 and matching FPGA cards and just want to use external clocking with them. Looking at page 26 in the user guide, it leaves a lot of questions unanswered. Just wondering if anyone can confirm which capacitors (and where are they on the board) need to be removed and what value capacitors need to be put onto the board.

ADC12J4000

  • 0
    TI__Mastermind 18095 points

    Michael:  We are looking into this and will respond shortly.  --RJH

  • 0 in reply to RJ Hopper
    TI__Mastermind 44680 points

    Hi Michael

    Please see the detailed instructions in the attached document. The capacitors that are installed in the new locations should be the same value (slightly larger in value is OK too) as the ones removed.

    /cfs-file/__key/communityserver-discussions-components-files/73/1057.Rework-for-External-Clocking.pdf

    Best regards,

    Jim B

  • 0 in reply to Jim Brinkhurst1
    Prodigy 180 points
    Thanks, I noticed that when you are moving C112->C123 and C113->C114, they are all the same capacitor so it doesn't matter.

    But regarding C32->C36 and C33->C30, the C32 and C33 are 4700pF and the C36 and C30 are 0.22uF, based on the BOM for the board. As the above instructions says to move the capacitor that would appear that contradicts the BOM??? What value should C36 and C30 be??
  • 0 in reply to Michael Robertson52
    TI__Mastermind 20541 points
    Hi Michael,

    I think you would be fine with moving C32,C33 to C30,C36's position. 4700pF would give a highpass filter with Fc of .6MHz and .22uF would a cutoff 14.46KHz. Both of these frequency are low enough to pass your clock signal without any issues.

    Regards,
    Neeraj Gill
  • 0 in reply to Neeraj Gill
    Prodigy 180 points
    Thanks Neeraj. I have modified the board now and while in principal it works with external clocking, a few problems were observed. Majority of the time the capture works fine but maybe 1/5 times the noisefloor rises from around 100dB to about -70dB, also sometimes a capture results in an error which pops up saying check the board etc. Sometimes dismissing the error and pressing capture again it works, other times I have to reset everything. Any ideas?
  • 0 in reply to Michael Robertson52
    TI__Mastermind 44680 points

    Hi Michael

    Please make sure that both of your RF generators used for clocking (one for the ADC DEVCLK and one for the LMK04828 input clock) are frequency locked using a common 10 MHz. reference. It is best to look at these on a high speed oscilloscope if possible.

    I have seen cases where the references were shared properly and the generators reported no errors, but the two generator outputs were not frequency locked.

    If the clocks are not frequency locked the JESD204B link will not be stable.

    Best regards,

    Jim B

  • 0 in reply to Jim Brinkhurst1
    Prodigy 180 points
    Hi Jim, yes they are frequency locked, using a common 10MHz. I haven't got a fast enough oscilloscope, so I turned the freq's down to 100MHz and 200MHz and everything looked fine. What am I looking for, would the phase between DEVCLK and LMCLK matter?
  • 0 in reply to Michael Robertson52
    TI__Mastermind 44680 points

    Hi Michael

    I'm not sure what is causing the problem, but here are a few other things to look into:

    1. If a lowpass or bandpass filter is used on the ADC DEVCLK, ensure the frequency of the filter is appropriate for the DEVCLK frequency you are using.
    2. What clock frequencies are you using?
    3. Set the RF generator used for the DEVCLK to be in the +6 to +9 dBm range.
    4. Set the RF generator used for the LMKCLK to be in the 0 to +6 dBm range.
    5. Confirm the proper ADC Output Sample rate value is entered in High Speed Data Converter Pro. This should be something like 3.2G for 3.2 GSPS, The wrong value here will configure the capture firmware incorrectly.
    6. Have you tried this on multiple ADC + Capture board combinations, or just a single one? Does changing to a different capture board or ADC board make a difference?

    That's all I can think of right now.

    Best regards,

    Jim B

  • 0 in reply to Jim Brinkhurst1
    Prodigy 180 points
    Hi Jim,
    1. Not using a BP filter, just a sig gen. I'll have a look at harmonics and ensure its not causing problems.
    2. DEVCLK is 4GHz and LMCLK is 2GHz.
    3 & 4..Both set to +11dBm as per the user guide??
    5. Set to 4GS/s
    6. Just one combination, before I made the board mod for ext clocking everything worked perfectly, doubt the capture board just stopped working.
  • 0 in reply to Michael Robertson52
    Prodigy 180 points
    All harmonics are at least -70dB below the signal, doubt that would be a problem.