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DAC39J84EVM Synthesizer Lock Time

Nick Kerkorian
Prodigy 40 points

Other Parts Discussed in Thread: DAC39J84, TRF3765, LMK04828, DAC38J84

Hello,

I'm looking to measure the lock time of the DAC39J84. Are there any external I/O on the DAC3XJXEVM board that we can use as a trigger for our E5052A Signal Analyzer?

Thank you,

Nick Kerkorian

  • 0
    TI__Guru* 83495 points
    Hi,

    The DAC EVM has the access to internal loop filter voltage at pin C9 through R133. You may solder a 1Mohm resistor to R133 and blue wire the other end to an SMA connector to your E5052A. This may help you with the loop analysis of the PLL loop (see figure 56 of d/s for PLL/VCO diagram). The LPF pin is basically a node connecting to the VCO for bias.

    The DAC is designed such that you should configure the PLL prior to the establishment of JESD204B link. I do not really see this being used as a synthesizer for frequency hopping applications. You may need to look into the TRF3765 or LMX family for a true synthesizer application.

    -Kang
  • 0 in reply to Kang Hsia
    TI__Guru* 83495 points
    You may also unmask alarm register config109 PLL_lock status through config5. If at any time the PLL is unlocked, the ALARM CMOS pin will be driven high or low to trigger the E5052. This is used as an interrupt. The ALARM pin polarity may be programmed depending on your need.

    -Kang
  • 0 in reply to Kang Hsia
    Prodigy 40 points
    Hi Kang,

    I'm sorry. I simply mean for calculating the time for the DAC's NCO to lock to a new frequency after updating it from an old one. Not for the PLL which generates the JESD clocks.
  • 0 in reply to Nick Kerkorian
    TI__Guru* 83495 points

    Nick,

    Ok, understood. The NCO and complex mixer block may be initialized by the SYSREF signal. You may tap off the SYSREF signal to the DAC38J84 at the LMK04828 SDCLKOUT1 output (R109, R108, i.e.). Keep in mind that this is a DC coupled signal with common mode of 0.5V, so be carefully on connecting this to the E5052. You probably need some sort of high Z connection to prevent DC bias problems at the LMK/DAC and E5052 side.

    In the GUI section, configure the LMK04828, SYSREF section to be single pulse mode (i.e. LMK04828 Controls -> SYSREF and SYNC-> SYSREF configuration -> pulse count). Be sure to disable the clock divider syncing and JESD204B link0/1 syncing to avoid interruptions to other critical blocks (i.e. DAC3xJ8x Controls -> Clocking ->  SYncing of clocking dividers, and also JESD block -> Link0 configuration -> how is SYSREF used)

    Keep in mind SYSREF signal will impact NCO operation and interrupt it upon edge detection of SYSREF. Be careful of any transients that may damage your equipment. Also, if your SYSREF is continuous, it must be integer divisible to the NCO frequency. Otherwise the NCO counter may not reset in the same cycle as SYSREF. See attached app note, section "SYSREF initialization for DSP blocks". This app note is in the process of being published.

    3175.DAC38J84 SYSREF Configuration1-8-2016.pdf

    -Kang